u-boot.git/drivers/Kconfig, branch v2020.10 Unnamed repository; edit this file 'description' to name the repository. xen: pvblock: Add initial support for para-virtualized block driver 2020-08-14T19:18:30+00:00 Anastasiia Lukianenko anastasiia_lukianenko@epam.com 2020-08-06T09:42:55+00:00 722bc5b5d901eafb96e8530cc7cf3036bff398a4 Add initial infrastructure for Xen para-virtualized block device. This includes compile-time configuration and the skeleton for the future driver implementation. Add new class UCLASS_PVBLOCK which is going to be a parent for virtual block devices. Add new interface type IF_TYPE_PVBLOCK. Implement basic driver setup by reading XenStore configuration. Signed-off-by: Andrii Anisov <andrii_anisov@epam.com> Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> 
Add initial infrastructure for Xen para-virtualized block device.
This includes compile-time configuration and the skeleton for
the future driver implementation.
Add new class UCLASS_PVBLOCK which is going to be a parent for
virtual block devices.
Add new interface type IF_TYPE_PVBLOCK.

Implement basic driver setup by reading XenStore configuration.

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
dm: button: add an uclass for button 2020-07-29T01:30:39+00:00 Philippe Reynes philippe.reynes@softathome.com 2020-07-24T16:19:45+00:00 30d66db78725e8396a3bd255cc51592c6cd7879d Add a new uclass for button that implements two functions: - button_get_by_label - button_get_status Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> 
Add a new uclass for button that implements two functions:
- button_get_by_label
- button_get_status

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
bus: uniphier-system-bus: add UniPhier System Bus driver 2020-07-11T12:30:21+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2020-07-09T06:08:18+00:00 e2bb0be2fc2276d33646545de342196de8c4040e Since commit 1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based drivers/net/smc911x.c is compiled, but it is never probed because the parent node lacks the DM-based driver. I need a skeleton driver to populate child devices (but the next commit will move more hardware settings to the this driver). I put this to drivers/bus/uniphier-system-bus.c because this is the same path as the driver in Linux kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
Since commit 1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based
drivers/net/smc911x.c is compiled, but it is never probed because the
parent node lacks the DM-based driver.

I need a skeleton driver to populate child devices (but the next commit
will move more hardware settings to the this driver).

I put this to drivers/bus/uniphier-system-bus.c because this is the
same path as the driver in Linux kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
dm: rng: Add random number generator(rng) uclass 2020-01-07T17:08:21+00:00 Sughosh Ganu sughosh.ganu@linaro.org 2019-12-28T18:28:27+00:00 a2487684003b0bc380955e1a38cdd71da3ca4366 Add a uclass for reading a random number seed from a random number generator device. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> 
Add a uclass for reading a random number seed from a random number
generator device.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
ufs: Add Initial Support for UFS subsystem 2019-10-24T00:47:12+00:00 Faiz Abbas faiz_abbas@ti.com 2019-10-15T12:54:36+00:00 7feafb0ae4f703874119bd90d53258134f850d37 Add Support for UFS Host Controller Interface (UFSHCI) for communicating with Universal Flash Storage (UFS) devices. The steps to initialize the host controller interface are the following: - Initiate the Host Controller Initialization process by writing to the Host controller enable register. - Configure the Host Controller base address registers by allocating a host memory space and related data structures. - Unipro link startup procedure - Check for connected device - Configure UFS host controller to process requests Also register this host controller as a SCSI host controller. Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported to U-boot. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> 
Add Support for UFS Host Controller Interface (UFSHCI) for communicating
with Universal Flash Storage (UFS) devices. The steps to initialize the
host controller interface are the following:

- Initiate the Host Controller Initialization process by writing to the
Host controller enable register.
- Configure the Host Controller base address registers by allocating a
host memory space and related data structures.
- Unipro link startup procedure
- Check for connected device
- Configure UFS host controller to process requests

Also register this host controller as a SCSI host controller.

Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported to
U-boot.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Drop PCMCIA 2019-08-11T23:27:41+00:00 Simon Glass sjg@chromium.org 2019-08-01T15:47:14+00:00 9e5616dea9db5e13ab3da1d5b414ce0bc7dc0afe This is no-longer used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> 
This is no-longer used in U-Boot and has not been converted to driver
model. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
drivers: pci_ep: Introduce UCLASS_PCI_EP uclass 2019-07-11T14:05:15+00:00 Ramon Fried ramon.fried@gmail.com 2019-04-27T08:15:21+00:00 914026d25848b856a669d629cb284c34843d707e Introduce new UCLASS_PCI_EP class for handling PCI endpoint devices, allowing to set various attributes of the PCI endpoint device, such as: * configuration space header * BAR definitions * outband memory mapping * start/stop PCI link Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Introduce new UCLASS_PCI_EP class for handling PCI endpoint
devices, allowing to set various attributes of the PCI endpoint
device, such as:
* configuration space header
* BAR definitions
* outband memory mapping
* start/stop PCI link

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
dm: cache: Create a uclass for cache 2019-05-05T12:48:50+00:00 Dinh Nguyen dinguyen@kernel.org 2019-04-23T21:55:03+00:00 84b124db3584d8b3f1a42c1506983323bce9983f The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
soc: ti: k3: add navss ringacc driver 2019-04-12T00:07:12+00:00 Grygorii Strashko grygorii.strashko@ti.com 2019-02-05T12:01:22+00:00 432f66fe731eab1c3318bd34a677f652a4be680f The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x SoCs. The RINGACC converts constant-address read and write accesses to equivalent read or write accesses to a circular data structure in memory. The RINGACC eliminates the need for each DMA controller which needs to access ring elements from having to know the current state of the ring (base address, current offset). The DMA controller performs a read or write access to a specific address range (which maps to the source interface on the RINGACC) and the RINGACC replaces the address for the transaction with a new address which corresponds to the head or tail element of the ring (head for reads, tail for writes). Since the RINGACC maintains the state, multiple DMA controllers or channels are allowed to coherently share the same rings as applicable. The RINGACC is able to place data which is destined towards software into cached memory directly. Supported ring modes: - Ring Mode - Messaging Mode - Credentials Mode - Queue Manager Mode TI-SCI integration: Texas Instrument's System Control Interface (TI-SCI) Message Protocol now has control over Ringacc module resources management (RM) and Rings configuration. The Ringacc driver manages Rings allocation by itself now and requests TI-SCI firmware to allocate and configure specific Rings only. It's done this way because, Linux driver implements two stage Rings allocation and configuration (allocate ring and configure ring) while TI-SCI Message Protocol supports only one combined operation (allocate+configure). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> 
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.

The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.

Supported ring modes:
 - Ring Mode
 - Messaging Mode
 - Credentials Mode
 - Queue Manager Mode

TI-SCI integration:

Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.

The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while TI-SCI Message
Protocol supports only one combined operation (allocate+configure).

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
x86: sandbox: pch: Add a CONFIG option for PCH 2019-02-20T07:25:30+00:00 Simon Glass sjg@chromium.org 2019-02-17T03:24:49+00:00 c882163b09b8a2c52e3dd8acd7d296d6d06d1f2e At present this uclass is selected only on x86. In order to add a test for it, it must also support sandbox. Create a new CONFIG_PCH option and enable it on x86 and sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>