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<title>u-boot.git/drivers/Makefile, branch v2016.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Add a reset driver framework/uclass</title>
<updated>2016-06-19T23:05:55+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-06-17T15:43:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89c1e2da78f82a09685006291ce8bb44f635fa25'/>
<id>89c1e2da78f82a09685006291ce8bb44f635fa25</id>
<content type='text'>
A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.

This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.

The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
A reset controller is a hardware module that controls reset signals that
affect other hardware modules or chips.

This patch defines a standard API that connects reset clients (i.e. the
drivers for devices affected by reset signals) to drivers for reset
controllers/providers. Initially, DT is the only supported method for
connecting the two.

The DT binding specification (reset.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/reset/reset.txt.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>verified-boot: Minimal support for booting U-Boot proper from SPL</title>
<updated>2016-06-12T17:14:58+00:00</updated>
<author>
<name>Teddy Reed</name>
<email>teddy.reed@gmail.com</email>
</author>
<published>2016-06-10T02:18:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=51c14cd128f4355514397dc3c8647fb14f7d8ff4'/>
<id>51c14cd128f4355514397dc3c8647fb14f7d8ff4</id>
<content type='text'>
This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.

The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256

In this example, SHA256 is the only selected hashing algorithm.

And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y

Signed-off-by: Teddy Reed &lt;teddy.reed@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Acked-by: Sumit Garg &lt;sumit.garg@nxp.com&gt;
</content>
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<pre>
This allows a board to configure verified boot within the SPL using
a FIT or FIT with external data. It also allows the SPL to perform
signature verification without needing relocation.

The board configuration will need to add the following feature defines:
CONFIG_SPL_CRYPTO_SUPPORT
CONFIG_SPL_HASH_SUPPORT
CONFIG_SPL_SHA256

In this example, SHA256 is the only selected hashing algorithm.

And the following booleans:
CONFIG_SPL=y
CONFIG_SPL_DM=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_FIT_SIGNATURE=y

Signed-off-by: Teddy Reed &lt;teddy.reed@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Acked-by: Sumit Garg &lt;sumit.garg@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add a mailbox driver framework/uclass</title>
<updated>2016-05-27T02:48:31+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-05-13T21:50:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6238935d018042d332aa7e90eae3addfeb11abdc'/>
<id>6238935d018042d332aa7e90eae3addfeb11abdc</id>
<content type='text'>
A mailbox is a hardware mechanism for transferring small message and/or
notifications between the CPU on which U-Boot runs and some other device
such as an auxilliary CPU running firmware or a hardware module.

This patch defines a standard API that connects mailbox clients to mailbox
providers (drivers). Initially, DT is the only supported method for
connecting the two.

The DT binding specification (mailbox.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A mailbox is a hardware mechanism for transferring small message and/or
notifications between the CPU on which U-Boot runs and some other device
such as an auxilliary CPU running firmware or a hardware module.

This patch defines a standard API that connects mailbox clients to mailbox
providers (drivers). Initially, DT is the only supported method for
connecting the two.

The DT binding specification (mailbox.txt) was taken from Linux kernel
v4.5's Documentation/devicetree/bindings/mailbox/mailbox.txt.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: mmc: spl: Use the legacy block interface in SPL</title>
<updated>2016-05-17T15:54:43+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-01T19:52:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0776167ec5541a2b4fa099dfea5a1aad2d4b7c72'/>
<id>0776167ec5541a2b4fa099dfea5a1aad2d4b7c72</id>
<content type='text'>
Bring this in for SPL so that we can use generic code for loading from
block devices.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Bring this in for SPL so that we can use generic code for loading from
block devices.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: usb: Drop the get_dev() function</title>
<updated>2016-05-17T15:54:43+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-01T17:36:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=57ebf67bad82da0b3ade1728fb39a64d1c29822f'/>
<id>57ebf67bad82da0b3ade1728fb39a64d1c29822f</id>
<content type='text'>
This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This function is implemented by the legacy block functions now. Drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: Add SPMI bus uclass</title>
<updated>2016-04-01T21:18:12+00:00</updated>
<author>
<name>Mateusz Kulikowski</name>
<email>mateusz.kulikowski@gmail.com</email>
</author>
<published>2016-03-31T21:12:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=04868b407b624c414805c9e9a79195eeb3a14829'/>
<id>04868b407b624c414805c9e9a79195eeb3a14829</id>
<content type='text'>
Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.

Signed-off-by: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.

Signed-off-by: Mateusz Kulikowski &lt;mateusz.kulikowski@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.</title>
<updated>2016-02-01T21:14:01+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9ffa7a35ef940b27813c11f68eb28a6b82696915'/>
<id>9ffa7a35ef940b27813c11f68eb28a6b82696915</id>
<content type='text'>
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker &lt;paul.thacker@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker &lt;paul.thacker@microchip.com&gt;
Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: Expand the uclass for Platform Controller Hubs (PCH)</title>
<updated>2016-01-24T04:07:17+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-19T03:19:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ca831f4933dc68d9ed1b6399cbda90068c520005'/>
<id>ca831f4933dc68d9ed1b6399cbda90068c520005</id>
<content type='text'>
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mvebu: Move SoC selection (A38X vs AXP) into Kconfig</title>
<updated>2016-01-14T13:08:59+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2015-12-21T12:56:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=81e33f4b65171a7dcb99a3efd9b3a45da129a21a'/>
<id>81e33f4b65171a7dcb99a3efd9b3a45da129a21a</id>
<content type='text'>
Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.

Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.

And CONFIG_DDR3 is removed, as its not referenced anywhere.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
</content>
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<pre>
Until now, the SoC selection for the ARCH_MVEBU platforms has been done
in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As
it needed to get selected for AXP and A38x based boards. This patch
now changes this to move the SoC selection to Kconfig. And also
uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x.
This makes things a bit clearer - especially for new board additions.

Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and
CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available
CONFIG_ARMADA_38X and CONFIG_ARMADA_XP.

And CONFIG_DDR3 is removed, as its not referenced anywhere.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Various Makefiles: Add SPDX-License-Identifier tags</title>
<updated>2015-11-10T14:19:52+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2015-11-10T01:06:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=da58dec866161e8ce73957fea463a8caad695000'/>
<id>da58dec866161e8ce73957fea463a8caad695000</id>
<content type='text'>
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
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