Smatch reported an issue with a test that was always true in that an
unsigned variable will always be >= to zero. This led to a closer look
at the code which showed that some static functions returned values that
were always discarded so make those functions return void. Also make
the passing of block counts in those functions always use lbaint_t.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>

First, the SATA_MV driver can only build on kirkwood or mvebu platforms
due to header requirements, so add that as a dependency here. Second,
SYS_SATA_MAX_DEVICE is also used by the API code so allow it to be
configured in that case.

Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

Use consistent lowercase hex prefix style in drivers/*

Does not change hex prefix case in allcaps uppercase style error messages

Signed-off-by: E Shattow <e@freeshell.de>

Jiaxun Yang <jiaxun.yang@flygoat.com> says:

This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.

I also converted the target to OF_UPSTREAM.

This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```

Link: https://lore.kernel.org/r/20240517-boston-v3-0-1ea7d23f4a1d@flygoat.com

Remove hard dependencies to arch headers, get clock from clk
subsystem if arch clock function is not available, align
compatible strings with devicetree binding.

No functional change on existing platforms, just get it build
on other platforms.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Ensure that we are using correct physical/virtual address for
DMA buffer write and hardware register settings.

The convention is: in ahci_ioports all pointers are virtual,
that will be converted to physical address when writing to
hardware registers or into sg/cmd_tbl.

Also fixed 64bit physical address support for dwc_ahsata, ensure
higher bits are written into registers/sg properly.

Use memalign for allocating aligned buffer in dwc_ahsata so we
don't have to do our own alignment in driver.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Tom Rini <trini@konsulko.com> says:

This series switches to always using $(PHASE_) in Makefiles when
building rather than $(PHASE_) or $(XPL_). It also starts on documenting
this part of the build, but as a follow-up we need to rename
doc/develop/spl.rst and expand on explaining things a bit.

Link: https://lore.kernel.org/r/20250401225851.1125678-1-trini@konsulko.com

It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini <trini@konsulko.com>

Caleb Connolly <caleb.connolly@linaro.org> says:

SCSI devices like UFS may maintain their own cache to speed up writes,
however this is lost on board reset (and may be lost on device removal
or reset by OS drivers).

Currently this can be worked around by "waiting for a while" after
writing data to disk, but of course this is not an acceptable solution.

Ideally U-Boot would have a mechanism to flush caches during board
reset, but until that logic is hooked up let's be sure that all writes
are actually propagated to the storage device so that we don't lose data
on board reset.

The same logic was already implemented just for the AHCI backend, this
duplicated logic has been removed and support for the SYNC_CACHE command
is added to AHCI.

This is particularly noticeable during capsule updates, since the update
file is deleted and the board is reset immediately afterwards which
resulted in the same capsule update being applied over and over again.

This specifically fixes Qualcomm SDM845 devices with UFS 2.1, but likely
all UFS devices that use a cache.

Link: https://lore.kernel.org/r/20250326-scsi-sync-on-write-v2-0-12ab05bd464b@linaro.org

The SCSI layer now issues a SYNC_CACHE command after every write to
ensure there is no data loss due to a board reset after write.

Implement support for this command and remove the same logic from the
ATA write path to be consistent with other SCSI backends.

Ranges are not supported and the whole cache will be flushed in all
cases.

This was done per iteration in ata_scsiop_read_write(), but it's not
clear why this was the case, calling it once for the entire write ought
to achieve the same result.

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>