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<title>u-boot.git/drivers/ata, branch v2022.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pci: Add mask parameter to dm_pci_map_bar()</title>
<updated>2022-05-03T22:33:29+00:00</updated>
<author>
<name>Andrew Scull</name>
<email>ascull@google.com</email>
</author>
<published>2022-04-21T16:11:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2635e3b50f8e646fc54c2bb15a017dea61a64a68'/>
<id>2635e3b50f8e646fc54c2bb15a017dea61a64a68</id>
<content type='text'>
Add a mask parameter to control the lookup of the PCI region from which
the mapping can be made.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
Add a mask parameter to control the lookup of the PCI region from which
the mapping can be made.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Map bars with offset and length</title>
<updated>2022-05-03T19:50:46+00:00</updated>
<author>
<name>Andrew Scull</name>
<email>ascull@google.com</email>
</author>
<published>2022-04-21T16:11:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=12507a2d2269f36d16232d78ec15e861d3fff2d7'/>
<id>12507a2d2269f36d16232d78ec15e861d3fff2d7</id>
<content type='text'>
Evolve dm_pci_map_bar() to include an offset and length parameter. These
allow a portion of the memory to be mapped and range checks to be
applied.

Passing both the offset and length as zero results in the previous
behaviour and this is used to migrate the previous callers.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
Evolve dm_pci_map_bar() to include an offset and length parameter. These
allow a portion of the memory to be mapped and range checks to be
applied.

Passing both the offset and length as zero results in the previous
behaviour and this is used to migrate the previous callers.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ahci: add PCI bindings for Marvell 88SE6121/45 SATA controllers</title>
<updated>2022-04-11T19:03:29+00:00</updated>
<author>
<name>Hajo Noerenberg</name>
<email>hajo-uboot@noerenberg.de</email>
</author>
<published>2022-03-28T13:49:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c3322a53f34f986ad9818df72707ebb59c9c8725'/>
<id>c3322a53f34f986ad9818df72707ebb59c9c8725</id>
<content type='text'>
Add AHCI PCI bindings for Marvell 88SE6121/45 SATA controllers.

The 88SE6121 controller is used, for example, in the Seagate Blackarmor NAS440 or the Iomega ix4-200d NAS.

As Pali Rohár explained [1], these controllers do not match the standard AHCI class code and therefore require an explizit PCI binding. The Linux kernel also uses this approach [2].

[1] https://lists.denx.de/pipermail/u-boot/2022-March/479197.html
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci.c?h=v5.17#n557

Signed-off-by: Hajo Noerenberg &lt;hajo-uboot@noerenberg.de&gt;
Reviewed-by: Pali Rohár &lt;pali@kernel.org&gt;
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<pre>
Add AHCI PCI bindings for Marvell 88SE6121/45 SATA controllers.

The 88SE6121 controller is used, for example, in the Seagate Blackarmor NAS440 or the Iomega ix4-200d NAS.

As Pali Rohár explained [1], these controllers do not match the standard AHCI class code and therefore require an explizit PCI binding. The Linux kernel also uses this approach [2].

[1] https://lists.denx.de/pipermail/u-boot/2022-March/479197.html
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci.c?h=v5.17#n557

Signed-off-by: Hajo Noerenberg &lt;hajo-uboot@noerenberg.de&gt;
Reviewed-by: Pali Rohár &lt;pali@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sata: call device_probe() after scanning</title>
<updated>2022-04-09T19:06:31+00:00</updated>
<author>
<name>AKASHI Takahiro</name>
<email>takahiro.akashi@linaro.org</email>
</author>
<published>2022-03-08T11:36:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c662edd6de9002176f62c05c6fe71bd5b4e84c4c'/>
<id>c662edd6de9002176f62c05c6fe71bd5b4e84c4c</id>
<content type='text'>
Every time a sata bus/port is scanned and a new device is detected,
we want to call device_probe() as it will give us a chance to run
additional post-processings for some purposes.

In particular, support for creating partitions on a device will be added.

Signed-off-by: AKASHI Takahiro &lt;takahiro.akashi@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Every time a sata bus/port is scanned and a new device is detected,
we want to call device_probe() as it will give us a chance to run
additional post-processings for some purposes.

In particular, support for creating partitions on a device will be added.

Signed-off-by: AKASHI Takahiro &lt;takahiro.akashi@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze</title>
<updated>2022-02-21T13:32:02+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-02-21T13:32:02+00:00</published>
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<id>24b628a8f844868adca897aae40af6f98cdbc26d</id>
<content type='text'>
Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
</content>
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<pre>
Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
</pre>
</div>
</content>
</entry>
<entry>
<title>scsi: ceva: Enable PHY and reset support</title>
<updated>2022-02-15T12:04:28+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2022-02-07T09:36:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f6f5451d469bb1541fe50dfe1661c114bc8b30b9'/>
<id>f6f5451d469bb1541fe50dfe1661c114bc8b30b9</id>
<content type='text'>
Add phy and reset support for ceva sata IP. Phy and reset are optional
properties that's why detect if description is available. If not just
continue with operation.
This code was tested on Xilinx Kria SOM kv260-revA with sata connector
populated.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Link: https://lore.kernel.org/r/eb3adf649be866aab19fc70ecc0fc8921545b1ac.1644226590.git.michal.simek@xilinx.com
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<pre>
Add phy and reset support for ceva sata IP. Phy and reset are optional
properties that's why detect if description is available. If not just
continue with operation.
This code was tested on Xilinx Kria SOM kv260-revA with sata connector
populated.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Link: https://lore.kernel.org/r/eb3adf649be866aab19fc70ecc0fc8921545b1ac.1644226590.git.michal.simek@xilinx.com
</pre>
</div>
</content>
</entry>
<entry>
<title>Convert CONFIG_SCSI_AHCI_PLAT et al to Kconfig</title>
<updated>2022-02-09T14:16:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-01-31T14:49:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=edca8cf72130c53fe399d1f354937c04efb96c7d'/>
<id>edca8cf72130c53fe399d1f354937c04efb96c7d</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_SCSI_AHCI_PLAT
   CONFIG_SYS_SCSI_MAX_SCSI_ID
   CONFIG_SYS_SCSI_MAX_LUN
   CONFIG_SYS_SATA_MAX_DEVICE

Drop CONFIG_SCSI for everything except the sandbox build. We only need
one build for tests.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This converts the following to Kconfig:
   CONFIG_SCSI_AHCI_PLAT
   CONFIG_SYS_SCSI_MAX_SCSI_ID
   CONFIG_SYS_SCSI_MAX_LUN
   CONFIG_SYS_SATA_MAX_DEVICE

Drop CONFIG_SCSI for everything except the sandbox build. We only need
one build for tests.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ahci: Make ahci drivers depend on AHCI</title>
<updated>2022-02-09T14:16:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-01-31T14:49:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f73a75618224b7e65a3e8a25b0b115bb1bee681b'/>
<id>f73a75618224b7e65a3e8a25b0b115bb1bee681b</id>
<content type='text'>
At present all ahci drivers depend on AHCI except for DWC_AHCI. But no
boards enable that without also enabling AHCI:

   /tools/moveconfig.py -f ~AHCI DWC_AHCI
   0 matches

Group them together and sort them in order by Kconfig name (except for
AHCI_MVEBU which uses a different naming convention).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
At present all ahci drivers depend on AHCI except for DWC_AHCI. But no
boards enable that without also enabling AHCI:

   /tools/moveconfig.py -f ~AHCI DWC_AHCI
   0 matches

Group them together and sort them in order by Kconfig name (except for
AHCI_MVEBU which uses a different naming convention).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sata: sata_sil: Only support BLK</title>
<updated>2022-02-09T14:16:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-01-31T14:49:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e7b02781f5a962f7642aa929789235eec0c65b4d'/>
<id>e7b02781f5a962f7642aa929789235eec0c65b4d</id>
<content type='text'>
No boards use this driver without CONFIG_BLK, so clean up the dead code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
No boards use this driver without CONFIG_BLK, so clean up the dead code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sata: Rearrange Kconfig for SATA</title>
<updated>2022-02-09T14:16:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-01-31T14:49:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6edb5dd388c749f03ec649ac6be98844abe0ea4f'/>
<id>6edb5dd388c749f03ec649ac6be98844abe0ea4f</id>
<content type='text'>
Move the SATA options inside an 'if SATA' part, so they are grouped.

Fix the 'Complient' typo while we are here.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
Move the SATA options inside an 'if SATA' part, so they are grouped.

Fix the 'Complient' typo while we are here.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
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