u-boot.git/drivers/block/Makefile, branch v2016.09 Unnamed repository; edit this file 'description' to name the repository. dm: blk: Add a legacy block interface 2016-05-17T15:54:43+00:00 Simon Glass sjg@chromium.org 2016-05-01T17:36:03+00:00 6eef6eac1fc137c97bf1993304ed83b8e483c80a There is quite a bit of duplicated common code related to block devices in the IDE and SCSI implementations. Create some helper functions that can be used to reduce the duplication. These rely on a linker list of interface-type drivers Signed-off-by: Simon Glass <sjg@chromium.org> 
There is quite a bit of duplicated common code related to block devices
in the IDE and SCSI implementations.

Create some helper functions that can be used to reduce the duplication.
These rely on a linker list of interface-type drivers

Signed-off-by: Simon Glass <sjg@chromium.org>
sandbox: Add dummy SATA functions 2016-05-17T15:54:43+00:00 Simon Glass sjg@chromium.org 2016-05-01T17:35:56+00:00 a31e2c93cb9eb1d4fe732b5586316235dad537ea Add some functions needed by the SATA code. This allows it to be compiled for sandbox, thus increasing build coverage. Signed-off-by: Simon Glass <sjg@chromium.org> 
Add some functions needed by the SATA code. This allows it to be compiled
for sandbox, thus increasing build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
sandbox: Add dummy SCSI functions 2016-05-17T15:54:43+00:00 Simon Glass sjg@chromium.org 2016-05-01T17:35:55+00:00 84d39cbd30a49390457232b44031e95abfa46e77 Add some functions needed by the SCSI code. This allows it to be compiled for sandbox, thus increasing build coverage. Signed-off-by: Simon Glass <sjg@chromium.org> 
Add some functions needed by the SCSI code. This allows it to be compiled
for sandbox, thus increasing build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
dm: Rename disk uclass to ahci 2016-05-17T15:54:43+00:00 Simon Glass sjg@chromium.org 2016-05-01T17:35:52+00:00 a219639d4216e59a0c55f0b7d2c8a21f9cb0bb06 This started as 'ahci' and was renamed to 'disk' during code review. But it seems that this is too generic. Now that we have a 'blk' uclass, we can use that as the generic piece, and revert to ahci for this. Signed-off-by: Simon Glass <sjg@chromium.org> 
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
block: Add support for Ceva sata 2016-04-04T18:28:39+00:00 Michal Simek michal.simek@xilinx.com 2015-09-30T15:26:55+00:00 679b994a2b56c65d53f94ab85baa68c252abdda4 Initial Ceva Sata init code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> 
Initial Ceva Sata init code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
drivers: block: add block device cache 2016-04-01T21:18:27+00:00 Eric Nelson eric@nelint.com 2016-03-28T17:05:44+00:00 e40cf34a29f1b248643731a11fb1c6f0520d016c Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: Eric Nelson <eric@nelint.com> 
Add a block device cache to speed up repeated reads of block devices by
various filesystems.

This small amount of cache can dramatically speed up filesystem
operations by skipping repeated reads of common areas of a block
device (typically directory structures).

This has shown to have some benefit on FAT filesystem operations of
loading a kernel and RAM disk, but more dramatic benefits on ext4
filesystems when the kernel and/or RAM disk are spread across
multiple extent header structures as described in commit fc0fc50.

The cache is implemented through a minimal list (block_cache) maintained
in most-recently-used order and count of the current number of entries
(cache_count). It uses a maximum block count setting to prevent copies
of large block reads and an upper bound on the number of cached areas.

The maximum number of entries in the cache defaults to 32 and the maximum
number of blocks per cache entry has a default of 2, which has shown to
produce the best results on testing of ext4 and FAT filesystems.

The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows
changing these values and can be used to tune for a particular filesystem
layout.

Signed-off-by: Eric Nelson <eric@nelint.com>
dm: blk: Add a block-device uclass 2016-03-14T21:34:50+00:00 Simon Glass sjg@chromium.org 2016-02-29T22:25:55+00:00 09d71aac7b530f03ec29cc9d5787047460a629ca Add a uclass for block devices. These provide block-oriented data access, supporting reading, writing and erasing of whole blocks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com> 
Add a uclass for block devices. These provide block-oriented data access,
supporting reading, writing and erasing of whole blocks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
ahci: Add a disk-controller uclass 2016-01-24T04:09:39+00:00 Simon Glass sjg@chromium.org 2016-01-17T23:11:34+00:00 e3b5f04143a859092d4e09f61e526790836714f2 Add a uclass ID for a disk controller. This can be used by AHCI/SATA or other controller types. There are no operations and no interface so far, but it is possible to probe a SATA device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a uclass ID for a disk controller. This can be used by AHCI/SATA or
other controller types. There are no operations and no interface so far,
but it is possible to probe a SATA device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
sata: Add SATA driver with DMA support for Marvell Kirkwood and Armada XP 2016-01-14T13:08:59+00:00 Tor Krill tor@excito.com 2015-12-03T11:38:02+00:00 169789dcb9b7ef1a97bf1aa245316687d7ced40f This patch adds a new SATA driver for the Marvell Kirkwood and Armada 370 / XP SoC's. This driver supports the SATA controller of some Mavell SoC's. Here a (most likely incomplete) list of the supported SoC's: - Kirkwood - Armada 370 - Armada XP This driver implementation is an alternative to the already available driver via the "ide" commands interface (drivers/block/mvsata_ide.c). But this driver only supports PIO mode and as this new driver also supports transfer via DMA, its much faster. Please note, that the newer SoC's (e.g. Armada 38x) are not supported by this driver. As they have an AHCI compatible SATA controller integrated. The original version of this driver was sent by Tor Krill to the U-Boot list a few years ago. Here the link: http://lists.denx.de/pipermail/u-boot/2010-June/073147.html Changes by Stefan: - Coding-style cleanup - Support for Armada XP added - MBUS window setup added - D-cache flush and invalidation added - works with dcache enabled on Armada XP - Removed mdelay() from ata_wait_register() and add timer based timeout detection to speed up the transfer Signed-off-by: Tor Krill <tor@excito.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com> 
This patch adds a new SATA driver for the Marvell Kirkwood and Armada
370 / XP SoC's.

This driver supports the SATA controller of some Mavell SoC's.
Here a (most likely incomplete) list of the supported SoC's:
- Kirkwood
- Armada 370
- Armada XP

This driver implementation is an alternative to the already available
driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
But this driver only supports PIO mode and as this new driver also
supports transfer via DMA, its much faster.

Please note, that the newer SoC's (e.g. Armada 38x) are not supported
by this driver. As they have an AHCI compatible SATA controller
integrated.

The original version of this driver was sent by Tor Krill to the U-Boot
list a few years ago. Here the link:

http://lists.denx.de/pipermail/u-boot/2010-June/073147.html

Changes by Stefan:
- Coding-style cleanup
- Support for Armada XP added
- MBUS window setup added
- D-cache flush and invalidation added - works with dcache enabled on
  Armada XP
- Removed mdelay() from ata_wait_register() and add timer based timeout
  detection to speed up the transfer

Signed-off-by: Tor Krill <tor@excito.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Tom Rini <trini@konsulko.com>
drivers: block: Remove the ata_piix driver 2015-07-15T00:03:20+00:00 Bin Meng bmeng.cn@gmail.com 2015-05-16T01:33:16+00:00 e1783b5ba3d32c0471a2b963ebec54e7e7cde264 This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>