u-boot.git/drivers/cache/Makefile, branch next Unnamed repository; edit this file 'description' to name the repository. driver: cache: Remove SiFive PL2 driver 2026-03-12T18:57:15+00:00 Nick Hu nick.hu@sifive.com 2026-01-19T05:55:23+00:00 61e2430360a592040357ab6a7241c29666b11e28 Under single core boot platform, the secondary cores won't enter the u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi. Signed-off-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Under single core boot platform, the secondary cores won't enter the
u-boot spl. Therefore we move the pl2 driver from u-boot to the Opensbi.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
global: Rename SPL_TPL_ to PHASE_ 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:54+00:00 5c10c8badf8233cac1593cd2bef4d0379ac9e5bd Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <sjg@chromium.org> 
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass <sjg@chromium.org>
andes: Unify naming policy for Andes related source 2024-05-14T10:50:47+00:00 Leo Yu-Chi Liang ycliang@andestech.com 2024-05-14T09:50:11+00:00 2b8dc36b4c515979da330a96d9fcc9bbbe5385fa Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
cache: add sifive private L2 cache driver 2023-12-27T09:28:57+00:00 Zong Li zong.li@sifive.com 2023-12-14T14:09:36+00:00 64e8482f1c94ab6e1fb4837a8744ca8a156c507e This driver is currently responsible for enabling the clock gating feature of SiFive pre core's private L2 cache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
cache: add sifive composable cache driver 2021-09-07T02:34:29+00:00 Zong Li zong.li@sifive.com 2021-09-01T07:01:39+00:00 43a21839285c1ba3b65534def898a2b5e2d46314 This driver is currently responsible for enabling all ccache ways. Composable cache could be configure as RAM or cache, we will use it as RAM at the beginning to put the u-boot SPL there. In u-boot proper phrase, we will use the composable cache as cache, and try to enable the cache ways. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> 
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
cache: Add Arteris Ncore cache coherent unit driver 2020-01-07T13:38:33+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-11-27T07:55:24+00:00 fec7ddc1907c1c86be6849de0fab7466b79cd834 Add Cache Coherency Unit (CCU) driver. CCU is to ensures consistency of shared data between multi masters in the system. Driver initializes CCU's directories and coherency agent interfaces in CCU IP. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 
Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.

Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
spl: Allow cache drivers to be used in SPL 2020-01-07T13:38:33+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-10-11T05:48:33+00:00 5c9c71b660a01d088ac66b7b8c1378915bcef68e Add an option for building cache drivers in SPL. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 
Add an option for building cache drivers in SPL.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
dm: cache: add v5l2 cache controller driver 2019-09-03T01:31:03+00:00 Rick Chen rick@andestech.com 2019-08-28T10:46:06+00:00 4fa4267d82d13eb45cc4202e4439de862e8cad0e Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
dm: cache: add the pl310 cache controller driver 2019-05-05T12:48:50+00:00 Dinh Nguyen dinguyen@kernel.org 2019-04-23T21:55:04+00:00 88ebf5830fe25cfdfbbee726cb36ea71b111173a Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
dm: cache: Create a uclass for cache 2019-05-05T12:48:50+00:00 Dinh Nguyen dinguyen@kernel.org 2019-04-23T21:55:03+00:00 84b124db3584d8b3f1a42c1506983323bce9983f The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>