u-boot.git/drivers/cache/cache-l2x0.c, branch v2023.04 Unnamed repository; edit this file 'description' to name the repository. cache: l2x0: Fix missing write to Auxiliary Control Register 2020-05-06T19:12:48+00:00 Ley Foon Tan ley.foon.tan@intel.com 2020-05-04T10:41:55+00:00 653f7c44677cd13bb106673bb7c46542e217fa13 In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 
In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override
bit") we removed writel to regs->pl310_aux_ctrl by accident.  This
commit restores it back.

Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit")
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
cache: l2x0: Fix write to incorrect shared-override bit 2020-04-24T20:40:09+00:00 Ley Foon Tan ley.foon.tan@intel.com 2020-04-17T06:45:35+00:00 f62782fb2999dd8109a3ffe9ee0a51e54ab034ab The existing code write bit-0 for shared attribute override enable bit. It should be bit-22 based on cache controller specification [1]. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 
The existing code write bit-0 for shared attribute override enable bit.
It should be bit-22 based on cache controller specification [1].

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
dm: cache: add the pl310 cache controller driver 2019-05-05T12:48:50+00:00 Dinh Nguyen dinguyen@kernel.org 2019-04-23T21:55:04+00:00 88ebf5830fe25cfdfbbee726cb36ea71b111173a Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>