u-boot.git/drivers/cache/cache-sifive-ccache.c, branch v2023.07.01Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/cache/cache-sifive-ccache.c?h=v2023.07.012023-04-20T08:08:44Zcache: starfive: Add StarFive JH7110 support2023-04-20T08:08:44ZYanhong Wangyanhong.wang@starfivetech.com2023-03-29T03:42:09Zurn:sha1:22c240273742befbf6791292dfdd6ebe63c2c09a
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
cache: sifive: Fix -Wint-to-pointer-cast warning2021-10-20T02:59:09ZBin Mengbmeng.cn@gmail.com2021-09-12T03:15:08Zurn:sha1:2fb91a2ea74e87d5e26e95f602c9f8e3951a35cf
The following warning is seen in cache-sifive-ccache.c in a 32-bit build:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
Fix by casting it with uintptr_t.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
cache: add sifive composable cache driver2021-09-07T02:34:29ZZong Lizong.li@sifive.com2021-09-01T07:01:39Zurn:sha1:43a21839285c1ba3b65534def898a2b5e2d46314
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>