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<title>u-boot.git/drivers/cache/cache-v5l2.c, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>dm: cache: add v5l2 cache controller driver</title>
<updated>2019-09-03T01:31:03+00:00</updated>
<author>
<name>Rick Chen</name>
<email>rick@andestech.com</email>
</author>
<published>2019-08-28T10:46:06+00:00</published>
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<id>4fa4267d82d13eb45cc4202e4439de862e8cad0e</id>
<content type='text'>
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen &lt;rick@andestech.com&gt;
Cc: KC Lin &lt;kclin@andestech.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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