u-boot.git/drivers/cache, branch v2020.01-rc1 Unnamed repository; edit this file 'description' to name the repository. dm: cache: add v5l2 cache controller driver 2019-09-03T01:31:03+00:00 Rick Chen rick@andestech.com 2019-08-28T10:46:06+00:00 4fa4267d82d13eb45cc4202e4439de862e8cad0e Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
dm: cache: Add enable and disable ops for sandbox and test 2019-09-03T01:31:03+00:00 Rick Chen rick@andestech.com 2019-08-28T10:46:05+00:00 abd858e5754c0f1e71aa86abde049d9ee81fda3e Add cache enable and disable ops for test coverage. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add cache enable and disable ops for test coverage.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
dm: cache: Add enable and disable ops for cache uclass 2019-09-03T01:31:03+00:00 Rick Chen rick@andestech.com 2019-08-28T10:46:04+00:00 4d0140ee1aa02c702846f47fe986a19ecc4318a6 Add cache enable/disable ops to the DM cache uclass driver Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add cache enable/disable ops to the DM cache uclass driver

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
dm: cache: add the pl310 cache controller driver 2019-05-05T12:48:50+00:00 Dinh Nguyen dinguyen@kernel.org 2019-04-23T21:55:04+00:00 88ebf5830fe25cfdfbbee726cb36ea71b111173a Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.

This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
dm: cache: Create a uclass for cache 2019-05-05T12:48:50+00:00 Dinh Nguyen dinguyen@kernel.org 2019-04-23T21:55:03+00:00 84b124db3584d8b3f1a42c1506983323bce9983f The cache UCLASS will be used for configure settings that can be found in a CPU's L2 cache controller. Add a uclass and a test for cache. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> 
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>