<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/cache, branch v2024.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>drivers: use dev_read_addr_ptr when cast to pointer</title>
<updated>2023-05-06T09:28:18+00:00</updated>
<author>
<name>Johan Jonker</name>
<email>jbx6244@gmail.com</email>
</author>
<published>2023-03-13T00:32:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a12a73b66476c48dfe5afd2c3711153d09feda6c'/>
<id>a12a73b66476c48dfe5afd2c3711153d09feda6c</id>
<content type='text'>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cache: starfive: Add StarFive JH7110 support</title>
<updated>2023-04-20T08:08:44+00:00</updated>
<author>
<name>Yanhong Wang</name>
<email>yanhong.wang@starfivetech.com</email>
</author>
<published>2023-03-29T03:42:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=22c240273742befbf6791292dfdd6ebe63c2c09a'/>
<id>22c240273742befbf6791292dfdd6ebe63c2c09a</id>
<content type='text'>
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.

Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
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<pre>
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.

Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver: cache-v5l2: Fix type casting warning on RV32</title>
<updated>2023-02-17T11:07:48+00:00</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-02-06T08:10:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=da24626d147cdd04e84f88c0196a0131fa22cee7'/>
<id>da24626d147cdd04e84f88c0196a0131fa22cee7</id>
<content type='text'>
This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
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<pre>
This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: ae350: dts: Update L2 cache compatible string</title>
<updated>2023-02-17T11:07:48+00:00</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-02-06T08:10:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c1b88196807e1dd797aea6cc7ddb0dce02b4e898'/>
<id>c1b88196807e1dd797aea6cc7ddb0dce02b4e898</id>
<content type='text'>
Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform</title>
<updated>2023-02-17T11:07:48+00:00</updated>
<author>
<name>Yu Chien Peter Lin</name>
<email>peterlin@andestech.com</email>
</author>
<published>2023-02-06T08:10:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=51415fa634d2ff0e2d10eeefb739cdb941d19412'/>
<id>51415fa634d2ff0e2d10eeefb739cdb941d19412</id>
<content type='text'>
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"</title>
<updated>2023-02-17T11:07:48+00:00</updated>
<author>
<name>Leo Yu-Chi Liang</name>
<email>ycliang@andestech.com</email>
</author>
<published>2023-02-06T08:10:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=55ca747f66742d15829f8706a633849d9013bab5'/>
<id>55ca747f66742d15829f8706a633849d9013bab5</id>
<content type='text'>
There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
Reviewed-by: Yu Chien Peter Lin &lt;peterlin@andestech.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: cache: ncore: Disable snoop filter</title>
<updated>2022-06-17T08:27:05+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@intel.com</email>
</author>
<published>2022-06-01T07:57:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d192adafebcd5e742a229aedbdcc7d6957d68f02'/>
<id>d192adafebcd5e742a229aedbdcc7d6957d68f02</id>
<content type='text'>
There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cache: sifive: Fix -Wint-to-pointer-cast warning</title>
<updated>2021-10-20T02:59:09+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-09-12T03:15:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2fb91a2ea74e87d5e26e95f602c9f8e3951a35cf'/>
<id>2fb91a2ea74e87d5e26e95f602c9f8e3951a35cf</id>
<content type='text'>
The following warning is seen in cache-sifive-ccache.c in a 32-bit build:

  warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Fix by casting it with uintptr_t.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The following warning is seen in cache-sifive-ccache.c in a 32-bit build:

  warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Fix by casting it with uintptr_t.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>WS cleanup: remove SPACE(s) followed by TAB</title>
<updated>2021-09-30T13:08:16+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2021-09-27T15:42:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0cf207ec01cbacae47585fcc26591dd2296507d6'/>
<id>0cf207ec01cbacae47585fcc26591dd2296507d6</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cache: add sifive composable cache driver</title>
<updated>2021-09-07T02:34:29+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2021-09-01T07:01:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=43a21839285c1ba3b65534def898a2b5e2d46314'/>
<id>43a21839285c1ba3b65534def898a2b5e2d46314</id>
<content type='text'>
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Rick Chen &lt;rick@andestech.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
