u-boot.git/drivers/cache, branch v2024.04

cache: add sifive private L2 cache driver

2023-12-27T09:28:57+00:00

This driver is currently responsible for enabling the clock gating
feature of SiFive pre core's private L2 cache.

Signed-off-by: Zong Li 
Reviewed-by: Leo Yu-Chi Liang

drivers: use dev_read_addr_ptr when cast to pointer

2023-05-06T09:28:18+00:00

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.

Signed-off-by: Johan Jonker 
Reviewed-by: Simon Glass

cache: starfive: Add StarFive JH7110 support

2023-04-20T08:08:44+00:00

This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.

Signed-off-by: Yanhong Wang 
Tested-by: Conor Dooley

driver: cache-v5l2: Fix type casting warning on RV32

2023-02-17T11:07:48+00:00

This patch fixes following warning for the riscv32 toolchain.

drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  122 |         regs = (struct l2cache *)dev_read_addr(dev);
      |                ^

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang

riscv: ae350: dts: Update L2 cache compatible string

2023-02-17T11:07:48+00:00

Update the compatible string of L2 cache.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Rick Chen

driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform

2023-02-17T11:07:48+00:00

The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.

Signed-off-by: Yu Chien Peter Lin 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Rick Chen

riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

2023-02-17T11:07:48+00:00

There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang 
Reviewed-by: Yu Chien Peter Lin 
Reviewed-by: Rick Chen

drivers: cache: ncore: Disable snoop filter

2022-06-17T08:27:05+00:00

There is hardware bug in NCORE CCU IP and it is causing an issue in the
coherent directory tracking of outstanding cache lines.
The workaround is disabling snoop filter.

Signed-off-by: Dinesh Maniyam 
Reviewed-by: Tien Fong Chee

cache: sifive: Fix -Wint-to-pointer-cast warning

2021-10-20T02:59:09+00:00

The following warning is seen in cache-sifive-ccache.c in a 32-bit build:

  warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Fix by casting it with uintptr_t.

Signed-off-by: Bin Meng 
Reviewed-by: Leo Yu-Chi Liang

WS cleanup: remove SPACE(s) followed by TAB

2021-09-30T13:08:16+00:00

Signed-off-by: Wolfgang Denk