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<title>u-boot.git/drivers/clk/Kconfig, branch v2018.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Kconfig?h=v2018.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Kconfig?h=v2018.01'/>
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<updated>2017-12-11T08:36:23Z</updated>
<entry>
<title>ARC: clk: introduce HSDK CGU clock driver</title>
<updated>2017-12-11T08:36:23Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2017-12-10T18:20:08Z</published>
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<id>urn:sha1:e80dac0ab83ccb1d54e2d91b93d27b54a7f6544f</id>
<content type='text'>
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c</title>
<updated>2017-11-30T03:30:50Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-11-15T12:14:48Z</published>
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<id>urn:sha1:f264e2357231066c2e626c737b88416f556dcd74</id>
<content type='text'>
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</content>
</entry>
<entry>
<title>clk: Kconfig: Add dependences of SPL_CLK</title>
<updated>2017-09-14T17:58:22Z</updated>
<author>
<name>Wenyou Yang</name>
<email>wenyou.yang@microchip.com</email>
</author>
<published>2017-07-31T07:21:57Z</published>
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<id>urn:sha1:0712b672d2a1f9a156c489b4dd7ce8354c2b3e1f</id>
<content type='text'>
The SPL_CLK config should depend on SPL &amp;&amp; SPL_DM.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@microchip.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: dm: Kconfig: split CLK support for SPL and TPL</title>
<updated>2017-08-13T15:12:20Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-06-28T23:45:01Z</published>
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<id>urn:sha1:7c819e7f2258be88cd48521ae796421ed2303fde</id>
<content type='text'>
Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>spl: dm: Kconfig: SPL_CLK depends on SPL_DM</title>
<updated>2017-08-13T15:12:20Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-06-28T23:44:07Z</published>
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<id>urn:sha1:f0776a551764bdb010a6fefd053c3aa88f1cf6bb</id>
<content type='text'>
SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>clk: rmobile: Add RCar Gen3 clock driver</title>
<updated>2017-08-02T19:26:24Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@gmail.com</email>
</author>
<published>2017-07-21T21:18:03Z</published>
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<id>urn:sha1:36c2ee4ce5192f0dd49b9616ba246bdad90e2546</id>
<content type='text'>
Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>dm: clk: add BCM6345 clock driver</title>
<updated>2017-05-10T14:16:09Z</updated>
<author>
<name>Álvaro Fernández Rojas</name>
<email>noltari@gmail.com</email>
</author>
<published>2017-05-07T18:13:01Z</published>
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<id>urn:sha1:5357eb95c02394ace9d2a26c516a07922f1a34aa</id>
<content type='text'>
This is a simplified version of linux/arch/mips/bcm63xx/clk.c

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: zynq: Add zynq clock framework driver</title>
<updated>2017-02-17T09:22:46Z</updated>
<author>
<name>Stefan Herbrechtsmeier</name>
<email>stefan.herbrechtsmeier@weidmueller.com</email>
</author>
<published>2017-01-17T15:27:29Z</published>
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<id>urn:sha1:3a64b2536487fe03d4d21d9cefb45b2c841a9d21</id>
<content type='text'>
Add a clock framework driver for the zynq platform. The driver is based
on the platform zynq clock driver but reworked to use static functions
instead of run-time generated objects even for unused clocks.
Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the
ps-clk-frequency from the device tree.

Signed-off-by: Stefan Herbrechtsmeier &lt;stefan.herbrechtsmeier@weidmueller.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>clk: zynqmp: Add clock driver support for zynqmp</title>
<updated>2017-01-10T09:18:12Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2016-11-15T10:45:41Z</published>
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<id>urn:sha1:128ec1fe6f5ee3a753326215732e6030e2c7c4d6</id>
<content type='text'>
Add basic clock driver support for zynqmp which
sets the required clock for GEM controller

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: boston: Providea simple driver for Boston board clocks</title>
<updated>2016-09-21T13:04:32Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:38Z</published>
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<id>urn:sha1:dd7c749474e0976cfc7e78dc9032d7fa8b9b9632</id>
<content type='text'>
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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