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<title>u-boot.git/drivers/clk/Kconfig, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Kconfig?h=v2018.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Kconfig?h=v2018.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-08-10T06:12:35Z</updated>
<entry>
<title>clk: Kconfig: Ascending order to sub directiory kconfigs</title>
<updated>2018-08-10T06:12:35Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2018-07-30T12:56:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cf6822574251c73133d1b4943fbe9b054f8f70e5'/>
<id>urn:sha1:cf6822574251c73133d1b4943fbe9b054f8f70e5</id>
<content type='text'>
sourcing of sub directiory kconfig files are not in
proper order, so keep them in ascending order.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>clk: Add Actions Semi OWL clock support</title>
<updated>2018-07-09T19:25:31Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2018-06-14T18:08:35Z</published>
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<id>urn:sha1:ae485b540f3b5555f5e043eaf2c8e859052f3b14</id>
<content type='text'>
This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.

Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>driver: clk: Add support for clocks on Armada 37xx</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:25Z</published>
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<id>urn:sha1:82a248df9af7057152a1359e7405585419accc1e</id>
<content type='text'>
The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
  - since setting rate is not supported, the driver computes the rates
    when probing and so subsequent calls to the .get_rate method do not
    read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

  - the .set_parent method theoretically could be supported on some clocks
    (the parent would have to be one of the TBG clocks)

  - the .set_rate method would have to try all the divider values to find
    the best approximation of a given rate, and it doesn't seem like
    this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: Add ICS8N3QV01 driver</title>
<updated>2018-05-08T22:50:23Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-04-27T12:53:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f0bcbe6c180485a9ff373cbe24cdaa415228a844'/>
<id>urn:sha1:f0bcbe6c180485a9ff373cbe24cdaa415228a844</id>
<content type='text'>
Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>clk: add driver for stm32mp1</title>
<updated>2018-03-19T20:14:22Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-03-12T09:46:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a6151916cbda43a36a69d3610f6588e0dbedb5dc'/>
<id>urn:sha1:a6151916cbda43a36a69d3610f6588e0dbedb5dc</id>
<content type='text'>
add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
  of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>ARC: clk: introduce HSDK CGU clock driver</title>
<updated>2017-12-11T08:36:23Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2017-12-10T18:20:08Z</published>
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<id>urn:sha1:e80dac0ab83ccb1d54e2d91b93d27b54a7f6544f</id>
<content type='text'>
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c</title>
<updated>2017-11-30T03:30:50Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-11-15T12:14:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f264e2357231066c2e626c737b88416f556dcd74'/>
<id>urn:sha1:f264e2357231066c2e626c737b88416f556dcd74</id>
<content type='text'>
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</content>
</entry>
<entry>
<title>clk: Kconfig: Add dependences of SPL_CLK</title>
<updated>2017-09-14T17:58:22Z</updated>
<author>
<name>Wenyou Yang</name>
<email>wenyou.yang@microchip.com</email>
</author>
<published>2017-07-31T07:21:57Z</published>
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<id>urn:sha1:0712b672d2a1f9a156c489b4dd7ce8354c2b3e1f</id>
<content type='text'>
The SPL_CLK config should depend on SPL &amp;&amp; SPL_DM.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@microchip.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: dm: Kconfig: split CLK support for SPL and TPL</title>
<updated>2017-08-13T15:12:20Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-06-28T23:45:01Z</published>
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<id>urn:sha1:7c819e7f2258be88cd48521ae796421ed2303fde</id>
<content type='text'>
Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>spl: dm: Kconfig: SPL_CLK depends on SPL_DM</title>
<updated>2017-08-13T15:12:20Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-06-28T23:44:07Z</published>
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<id>urn:sha1:f0776a551764bdb010a6fefd053c3aa88f1cf6bb</id>
<content type='text'>
SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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