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<title>u-boot.git/drivers/clk/Makefile, branch next</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=next</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=next'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2026-08-02T20:15:37Z</updated>
<entry>
<title>clk: rs9: Add Renesas 9-series PCIe clock generator driver</title>
<updated>2026-08-02T20:15:37Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2026-07-19T18:11:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=99203d9dac5246937854fa41677365c66d2a2264'/>
<id>urn:sha1:99203d9dac5246937854fa41677365c66d2a2264</id>
<content type='text'>
Add driver for Renesas 9-series PCIe clock generators. This driver
is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C
PCIe clock generators.

The driver is capable of configuring per-chip spread spectrum mode
and output amplitude, as well as per-output slew rate.

Losely based on Linux 7.1 commit
5ec820fc28d0 ("clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841")

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>clk: spacemit: Add support for K1 SoC</title>
<updated>2026-07-21T08:31:10Z</updated>
<author>
<name>Junhui Liu</name>
<email>junhui.liu@pigmoral.tech</email>
</author>
<published>2026-05-27T02:45:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3aa2882a3e1a72dbc597022c4f1a093e00c2400e'/>
<id>urn:sha1:3aa2882a3e1a72dbc597022c4f1a093e00c2400e</id>
<content type='text'>
The K1 SoC exposes four clock providers in the kernel mainline DT: one
PLL controller ("spacemit,k1-pll") and three syscon clock nodes
("spacemit,k1-syscon-{mpmu,apbc,apmu}"). Register a separate
U_BOOT_DRIVER for each.

The controllers register clocks into a single CCF namespace, and a clock
in one controller may parent off a clock owned by another, so a
controller must register only after the controllers that own its parents
have probed. Each probe forces its parent controllers up by driver:

    MPMU &lt;- PLL
    APMU &lt;- PLL, MPMU
    APBC &lt;- PLL, MPMU, APMU

Signed-off-by: Junhui Liu &lt;junhui.liu@pigmoral.tech&gt;
Signed-off-by: Raymond Mao &lt;raymond.mao@riscstar.com&gt;
Signed-off-by: Guodong Xu &lt;guodong@riscstar.com&gt;
</content>
</entry>
<entry>
<title>clk: imx: don't build i.MX/RTxxxx code for all users of CCF</title>
<updated>2026-06-05T15:55:39Z</updated>
<author>
<name>Alexander Sverdlin</name>
<email>alexander.sverdlin@siemens.com</email>
</author>
<published>2026-05-29T16:39:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e80108c966f3ce3b1194a5b43d589cceb4c8ec54'/>
<id>urn:sha1:e80108c966f3ce3b1194a5b43d589cceb4c8ec54</id>
<content type='text'>
When commit 1d7993d1d0ef
("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)")
introduced the parts of Linux Common Clock Framework, it was done for i.MX6
only and even had "depends on SPL_CLK_IMX6Q" conditions. Since commit
ccab06689aa2 ("clk: imx: expose CCF entry for all") the framework can be
reused with SoCs of other vendors (say, TI), but NXP SoC-specific code is
still being build. It is especially problematic for size-constrained SPL
images on TI AM62x.

Make the build of the i.MX/RTxxxx code not only dependent on
CONFIG_$(PHASE_)CLK_CCF, but also on CONFIG_MACH_IMX options which shall
cover the i.MX platform users.

This saves 2264 bytes on 32-bit ARM platforms [using CCF].

Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Alexander Sverdlin &lt;alexander.sverdlin@siemens.com&gt;
</content>
</entry>
<entry>
<title>clk: thead: Port clock controller driver of TH1520 SoC</title>
<updated>2025-05-21T08:49:57Z</updated>
<author>
<name>Yao Zi</name>
<email>ziyao@disroot.org</email>
</author>
<published>2025-05-16T03:05:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e6bfa6fc94f655545f4c79b9a9939cfeb97a3a89'/>
<id>urn:sha1:e6bfa6fc94f655545f4c79b9a9939cfeb97a3a89</id>
<content type='text'>
The driver is adapted from Linux kernel's version of clk-th1520-ap.c,
with only output clocks for external sensors, which are barely useful in
bootloaders, removed.

Same as the mainline driver, it currently lacks of ability to enable and
reconfigure PLLs, which could be implemented later.

Signed-off-by: Yao Zi &lt;ziyao@disroot.org&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>clk: airoha: Add support for Airoha AN7581 SoC clock</title>
<updated>2025-04-01T14:44:51Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2025-03-14T18:59:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d0b81afb5ec9d2d8a3f11bfc827f2f24c32d47ec'/>
<id>urn:sha1:d0b81afb5ec9d2d8a3f11bfc827f2f24c32d47ec</id>
<content type='text'>
Add support for Airoha AN7581 SoC clock driver. This mainly needed for
eMMC support to correctly get the current clock applied.

Based on the Linux clk-en7523.c but majorly reworked for U-Boot that
doesn't require CCF subsystem.

Major modification, support for set_rate, realtime get_rate and split
for reset part to a different driver.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: add stub clock driver</title>
<updated>2025-02-26T13:16:40Z</updated>
<author>
<name>Caleb Connolly</name>
<email>caleb.connolly@linaro.org</email>
</author>
<published>2025-02-10T16:27:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d31a3bd08ed46c51cdc5f5f126f2a721c5425bfb'/>
<id>urn:sha1:d31a3bd08ed46c51cdc5f5f126f2a721c5425bfb</id>
<content type='text'>
Add a stub clock driver which can be used to bind clock controllers
which aren't required for the platform to boot, but which are needed for
U-Boot drivers to work.

In addition, add a NOP parent driver to allow for binding the parent
nodes of the clock.

Initially this driver supports a Qualcomm platform where the MMC driver
tries to fetch the RPM clock controller, which is not actually required
for the device to work.

Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Acked-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>global: Rename SPL_TPL_ to PHASE_</title>
<updated>2024-10-11T17:44:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c10c8badf8233cac1593cd2bef4d0379ac9e5bd'/>
<id>urn:sha1:5c10c8badf8233cac1593cd2bef4d0379ac9e5bd</id>
<content type='text'>
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC</title>
<updated>2024-09-11T12:32:06Z</updated>
<author>
<name>Kongyang Liu</name>
<email>seashell11234455@gmail.com</email>
</author>
<published>2024-06-11T09:41:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5f364e072e76550b3c6d1b1f7711352ec7b14d7b'/>
<id>urn:sha1:5f364e072e76550b3c6d1b1f7711352ec7b14d7b</id>
<content type='text'>
Add clock controller driver for sophgo cv1800b SoC

Signed-off-by: Kongyang Liu &lt;seashell11234455@gmail.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03de305ec48b0bb28554372abb40ccd46dbe0bf9'/>
<id>urn:sha1:03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d678a59d2d719da9e807495b4b021501f2836ca5'/>
<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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