u-boot.git/drivers/clk/Makefile, branch v2017.03

aspeed: Add basic ast2500-specific drivers and configuration

2017-01-28T19:04:29Z

Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass

clk: zynqmp: Add clock driver support for zynqmp

2017-01-10T09:18:12Z

Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Simon Glass

clk: boston: Providea simple driver for Boston board clocks

2016-09-21T13:04:32Z

Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: Paul Burton Reviewed-by: Simon Glass

Merge branch 'master' of git://git.denx.de/u-boot-atmel

2016-08-15T21:31:23Z

clk: at91: Add clock driver

2016-08-15T20:12:00Z

The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass

clock: add Tegra186 clock driver

2016-08-15T17:26:13Z

In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren

move: rockchip: move clock drivers into a subdirectory

2016-08-05T23:56:08Z

With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: Simon Glass Signed-off-by: Heiko Stuebner Acked-by: Simon Glass Updated for rk3399: Signed-off-by: Simon Glass

rk3399: add basic soc driver

2016-08-05T23:56:07Z

This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang Acked-by: Simon Glass

clk: convert API to match reset/mailbox style

2016-06-19T23:05:55Z

The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren Acked-by: Simon Glass

clk: exynos: add clock driver for Exynos7420 Soc

2016-05-25T01:00:18Z

Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver. Cc: Minkyu Kang Cc: Simon Glass Signed-off-by: Thomas Abraham Reviewed-by: Simon Glass Signed-off-by: Minkyu Kang