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<title>u-boot.git/drivers/clk/Makefile, branch v2017.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2017.05</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2017.05'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2017-03-17T18:15:12Z</updated>
<entry>
<title>clk: stm32f7: add clock driver for stm32f7 family</title>
<updated>2017-03-17T18:15:12Z</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-02-12T18:25:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=712f99a5ddc404f8c6eac481cfe19f82ca2ecb4f'/>
<id>urn:sha1:712f99a5ddc404f8c6eac481cfe19f82ca2ecb4f</id>
<content type='text'>
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: zynq: Add zynq clock framework driver</title>
<updated>2017-02-17T09:22:46Z</updated>
<author>
<name>Stefan Herbrechtsmeier</name>
<email>stefan.herbrechtsmeier@weidmueller.com</email>
</author>
<published>2017-01-17T15:27:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3a64b2536487fe03d4d21d9cefb45b2c841a9d21'/>
<id>urn:sha1:3a64b2536487fe03d4d21d9cefb45b2c841a9d21</id>
<content type='text'>
Add a clock framework driver for the zynq platform. The driver is based
on the platform zynq clock driver but reworked to use static functions
instead of run-time generated objects even for unused clocks.
Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the
ps-clk-frequency from the device tree.

Signed-off-by: Stefan Herbrechtsmeier &lt;stefan.herbrechtsmeier@weidmueller.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>aspeed: Add basic ast2500-specific drivers and configuration</title>
<updated>2017-01-28T19:04:29Z</updated>
<author>
<name>maxims@google.com</name>
<email>maxims@google.com</email>
</author>
<published>2017-01-18T21:44:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=14e4b14979574a6b31f4e3037f81d5c66a8ae7b8'/>
<id>urn:sha1:14e4b14979574a6b31f4e3037f81d5c66a8ae7b8</id>
<content type='text'>
Clock Driver

This driver is ast2500-specific and is not compatible with earlier
versions of this chip. The differences are not that big, but they are
in somewhat random places, so making it compatible with ast2400 is not
worth the effort at the moment.

SDRAM MC driver

The driver is very ast2500-specific and is completely incompatible
with previous versions of the chip.

The memory controller is very poorly documented by Aspeed in the
datasheet, with any mention of the whole range of registers missing. The
initialization procedure has been basically taken from Aspeed SDK, where
it is implemented in assembly. Here it is rewritten in C, with very limited
understanding of what exactly it is doing.
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: zynqmp: Add clock driver support for zynqmp</title>
<updated>2017-01-10T09:18:12Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2016-11-15T10:45:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=128ec1fe6f5ee3a753326215732e6030e2c7c4d6'/>
<id>urn:sha1:128ec1fe6f5ee3a753326215732e6030e2c7c4d6</id>
<content type='text'>
Add basic clock driver support for zynqmp which
sets the required clock for GEM controller

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: boston: Providea simple driver for Boston board clocks</title>
<updated>2016-09-21T13:04:32Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dd7c749474e0976cfc7e78dc9032d7fa8b9b9632'/>
<id>urn:sha1:dd7c749474e0976cfc7e78dc9032d7fa8b9b9632</id>
<content type='text'>
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-atmel</title>
<updated>2016-08-15T21:31:23Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-08-15T21:31:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0fcb9f07a1d086fc6951c08d2fc1cf6048bd54e2'/>
<id>urn:sha1:0fcb9f07a1d086fc6951c08d2fc1cf6048bd54e2</id>
<content type='text'>
</content>
</entry>
<entry>
<title>clk: at91: Add clock driver</title>
<updated>2016-08-15T20:12:00Z</updated>
<author>
<name>Wenyou Yang</name>
<email>wenyou.yang@atmel.com</email>
</author>
<published>2016-07-20T09:55:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9e5935c04e891abb38a92a893f3457cdf304ef4f'/>
<id>urn:sha1:9e5935c04e891abb38a92a893f3457cdf304ef4f</id>
<content type='text'>
The patch is referred to at91 clock driver of Linux, to make
the clock node descriptions in DT aligned with the Linux's.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clock: add Tegra186 clock driver</title>
<updated>2016-08-15T17:26:13Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-08-08T17:28:24Z</published>
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<id>urn:sha1:d9fd7008f48ba3361133e3b901322a724fd2aced</id>
<content type='text'>
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>move: rockchip: move clock drivers into a subdirectory</title>
<updated>2016-08-05T23:56:08Z</updated>
<author>
<name>Heiko Stübner</name>
<email>heiko@sntech.de</email>
</author>
<published>2016-07-29T12:47:21Z</published>
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<id>urn:sha1:aff8795c01c39318eb07b4bf0cd7f170ff67d591</id>
<content type='text'>
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.

Suggested-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Updated for rk3399:
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>rk3399: add basic soc driver</title>
<updated>2016-08-05T23:56:07Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2016-07-29T02:35:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b0b3c86521e0fe4cca3676adfc0b937d77456f9e'/>
<id>urn:sha1:b0b3c86521e0fe4cca3676adfc0b937d77456f9e</id>
<content type='text'>
This patch add driver for:
- clock driver including set_rate for cpu, mmc, vop, I2C.
- sysreset driver
- grf syscon driver

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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