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<title>u-boot.git/drivers/clk/Makefile, branch v2018.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2018.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2018.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-06-19T11:31:47Z</updated>
<entry>
<title>clk: add Amlogic meson clock driver</title>
<updated>2018-06-19T11:31:47Z</updated>
<author>
<name>Beniamino Galvani</name>
<email>b.galvani@gmail.com</email>
</author>
<published>2018-06-14T11:43:39Z</published>
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<id>urn:sha1:c0fc1e215c6117b159bb9ca736d3e3338bbc028b</id>
<content type='text'>
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>driver: clk: Add support for clocks on Armada 37xx</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:25Z</published>
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<id>urn:sha1:82a248df9af7057152a1359e7405585419accc1e</id>
<content type='text'>
The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
  - since setting rate is not supported, the driver computes the rates
    when probing and so subsequent calls to the .get_rate method do not
    read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

  - the .set_parent method theoretically could be supported on some clocks
    (the parent would have to be one of the TBG clocks)

  - the .set_rate method would have to try all the divider values to find
    the best approximation of a given rate, and it doesn't seem like
    this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: Add ICS8N3QV01 driver</title>
<updated>2018-05-08T22:50:23Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-04-27T12:53:15Z</published>
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<id>urn:sha1:f0bcbe6c180485a9ff373cbe24cdaa415228a844</id>
<content type='text'>
Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>clk: add driver for stm32mp1</title>
<updated>2018-03-19T20:14:22Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-03-12T09:46:15Z</published>
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<id>urn:sha1:a6151916cbda43a36a69d3610f6588e0dbedb5dc</id>
<content type='text'>
add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
  of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>clk: Makefile: Sort entries alphabetically</title>
<updated>2018-01-21T17:01:02Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-01-15T10:06:54Z</published>
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<id>urn:sha1:fcca9db8192f3143c309bb7abc666d47c9c96aa4</id>
<content type='text'>
The Makefile entries in the clk driver directory were not alphabetically
sorted. Correct this.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>ARC: clk: introduce HSDK CGU clock driver</title>
<updated>2017-12-11T08:36:23Z</updated>
<author>
<name>Eugeniy Paltsev</name>
<email>Eugeniy.Paltsev@synopsys.com</email>
</author>
<published>2017-12-10T18:20:08Z</published>
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<id>urn:sha1:e80dac0ab83ccb1d54e2d91b93d27b54a7f6544f</id>
<content type='text'>
Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev &lt;Eugeniy.Paltsev@synopsys.com&gt;
Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c</title>
<updated>2017-11-30T03:30:50Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-11-15T12:14:48Z</published>
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<id>urn:sha1:f264e2357231066c2e626c737b88416f556dcd74</id>
<content type='text'>
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
</content>
</entry>
<entry>
<title>dm: clk: add clk driver support for stm32h7 SoCs</title>
<updated>2017-09-22T11:40:01Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-09-13T16:00:06Z</published>
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<id>urn:sha1:4c3aebd56a035740f04fce44ce6c398afbb5ad86</id>
<content type='text'>
This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>spl: dm: Kconfig: split CLK support for SPL and TPL</title>
<updated>2017-08-13T15:12:20Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-06-28T23:45:01Z</published>
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<id>urn:sha1:7c819e7f2258be88cd48521ae796421ed2303fde</id>
<content type='text'>
Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>clk: rmobile: Add RCar Gen3 clock driver</title>
<updated>2017-08-02T19:26:24Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@gmail.com</email>
</author>
<published>2017-07-21T21:18:03Z</published>
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<id>urn:sha1:36c2ee4ce5192f0dd49b9616ba246bdad90e2546</id>
<content type='text'>
Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
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