u-boot.git/drivers/clk/Makefile, branch v2018.09

clk: socfpga: Add initial Arria10 clock driver

2018-08-13T20:35:42+00:00

Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Ley Foon Tan

clk: Add Actions Semi OWL clock support

2018-07-09T19:25:31+00:00

This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.

Signed-off-by: Manivannan Sadhasivam 
Reviewed-by: Simon Glass

clk: add Amlogic meson clock driver

2018-06-19T11:31:47+00:00

Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.

Signed-off-by: Beniamino Galvani 
Signed-off-by: Neil Armstrong

driver: clk: Add support for clocks on Armada 37xx

2018-05-14T08:00:15+00:00

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
  - since setting rate is not supported, the driver computes the rates
    when probing and so subsequent calls to the .get_rate method do not
    read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

  - the .set_parent method theoretically could be supported on some clocks
    (the parent would have to be one of the TBG clocks)

  - the .set_rate method would have to try all the divider values to find
    the best approximation of a given rate, and it doesn't seem like
    this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun 
Reviewed-by: Stefan Roese 
Signed-off-by: Stefan Roese

clk: Add ICS8N3QV01 driver

2018-05-08T22:50:23+00:00

Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six

clk: add driver for stm32mp1

2018-03-19T20:14:22+00:00

add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
  of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay

clk: Makefile: Sort entries alphabetically

2018-01-21T17:01:02+00:00

The Makefile entries in the clk driver directory were not alphabetically
sorted. Correct this.

Reviewed-by: Simon Glass 
Signed-off-by: Mario Six

ARC: clk: introduce HSDK CGU clock driver

2017-12-11T08:36:23+00:00

Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Alexey Brodkin

clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c

2017-11-30T03:30:50+00:00

Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard 
Reviewed-by: Vikas Manocha

dm: clk: add clk driver support for stm32h7 SoCs

2017-09-22T11:40:01+00:00

This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

Signed-off-by: Patrice Chotard 
Reviewed-by: Simon Glass