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<title>u-boot.git/drivers/clk/Makefile, branch v2019.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2019.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2019.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-11-29T20:16:58Z</updated>
<entry>
<title>Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic</title>
<updated>2018-11-29T20:16:58Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-11-29T14:33:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93e72ac472b537bb4b0c6a97a7e6aab2b37860c6'/>
<id>urn:sha1:93e72ac472b537bb4b0c6a97a7e6aab2b37860c6</id>
<content type='text'>
Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
</content>
</entry>
<entry>
<title>clk: MediaTek: add clock driver for MT7629 SoC.</title>
<updated>2018-11-29T04:04:51Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-11-15T02:07:54Z</published>
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<id>urn:sha1:0bd7dc74d2ffee99b931606b94469f9c9ab9bbf1</id>
<content type='text'>
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.

- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.

We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: Add clock driver for AXG</title>
<updated>2018-11-26T13:40:52Z</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2018-09-07T15:25:13Z</published>
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<id>urn:sha1:f6eb68b978fdb9b109ece3c71e2cc19d041103c5</id>
<content type='text'>
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>drivers: cosmetic: Convert SPDX license tags to Linux Kernel style</title>
<updated>2018-10-28T13:26:39Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-10-26T07:02:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=22929e1266e9a61048bfaef381ad4fb2e2fc3ef5'/>
<id>urn:sha1:22929e1266e9a61048bfaef381ad4fb2e2fc3ef5</id>
<content type='text'>
Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>clk: imx: add clk driver for i.MX8QXP</title>
<updated>2018-10-22T10:59:01Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2018-10-18T12:28:30Z</published>
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<id>urn:sha1:f77d441091a277920d893c82c5811c552385af57</id>
<content type='text'>
Add clk driver for i.MX8QXP. This basic version supports clk
enable/disable/get_rate/set_rate operations for I2C, ENET,
SDHC0 and UART clocks.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: Add support for Arm's Versatile Express OSC clock generators</title>
<updated>2018-09-30T17:00:34Z</updated>
<author>
<name>Liviu Dudau</name>
<email>Liviu.Dudau@foss.arm.com</email>
</author>
<published>2018-09-17T16:50:00Z</published>
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<id>urn:sha1:a71e907c4dbeee69b9b70e266ccc1e7d760ef9c1</id>
<content type='text'>
The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Express config bus. The generators are quite often being controlled
by some MCU and the config bus offers a uniform way of exposing them.

Signed-off-by: Liviu Dudau &lt;liviu.dudau@foss.arm.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: Add MPC83xx clock driver</title>
<updated>2018-09-18T06:01:18Z</updated>
<author>
<name>Mario Six</name>
<email>mario.six@gdsys.cc</email>
</author>
<published>2018-08-06T08:23:36Z</published>
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<id>urn:sha1:07d538d2814fa03be243c71879372f4263030b78</id>
<content type='text'>
Add a clock driver for the MPC83xx architecture.

Signed-off-by: Mario Six &lt;mario.six@gdsys.cc&gt;
</content>
</entry>
<entry>
<title>clk: Introduce TI System Control Interface (TI SCI) clock driver</title>
<updated>2018-09-11T12:32:55Z</updated>
<author>
<name>Andreas Dannenberg</name>
<email>dannenberg@ti.com</email>
</author>
<published>2018-08-27T10:27:43Z</published>
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<id>urn:sha1:e585bef17f9cc22ff82398654e8dfed8e5f39100</id>
<content type='text'>
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Signed-off-by: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>clk: socfpga: Add initial Arria10 clock driver</title>
<updated>2018-08-13T20:35:42Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2018-07-31T15:58:07Z</published>
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<id>urn:sha1:f9f016adcdc686bf3c50399492d579a024ed7520</id>
<content type='text'>
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;chin.liang.see@intel.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
</entry>
<entry>
<title>clk: Add Actions Semi OWL clock support</title>
<updated>2018-07-09T19:25:31Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2018-06-14T18:08:35Z</published>
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<id>urn:sha1:ae485b540f3b5555f5e043eaf2c8e859052f3b14</id>
<content type='text'>
This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.

Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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