u-boot.git/drivers/clk/Makefile, branch v2019.10

clk: add composite clk support

2019-07-31T07:20:51Z

Import clk composite clk support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan

clk: add clk-gate support

2019-07-31T07:20:51Z

Import clk-gate support from Linux Kernel 5.1-rc5 Signed-off-by: Peng Fan

Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

2019-07-27T13:35:05Z

u-boot-imx-20190719 - CCF for i.MX6 - nandbcb command to write SPL into NAND - Switch to DM (i.MX28) - Boards: Toradex, engicam, DH - Fixes for i.MX8 - Fixes for i.MX7ULP Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504

clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]

2019-07-19T12:50:30Z

This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: Lukasz Majewski

clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)

2019-07-19T12:50:30Z

This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski

clk: sifive: Factor-out PLL library as separate module

2019-07-19T06:24:51Z

To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: Anup Patel Reviewed-by: Bin Meng

clk: create meson directory and move related drivers

2019-04-23T09:19:09Z

In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong

clk: Add fixed-factor clock driver

2019-02-27T01:12:33Z

This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Simon Glass

clk: Add SiFive FU540 PRCI clock driver

2019-02-27T01:12:33Z

Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf

clk: Add Allwinner A64 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard