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<title>u-boot.git/drivers/clk/Makefile, branch v2020.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2020.04</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2020.04'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2020-02-07T14:41:24Z</updated>
<entry>
<title>x86: Add a clock driver for Intel devices</title>
<updated>2020-02-07T14:41:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-06T16:54:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b4d00b256e3c784de4a33a40f4cd28a94ee2a80c'/>
<id>urn:sha1:b4d00b256e3c784de4a33a40f4cd28a94ee2a80c</id>
<content type='text'>
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.

This driver can be expanded later as needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: add clock driver for MediaTek MT76x8 platform</title>
<updated>2019-10-25T15:20:44Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2019-09-25T09:45:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=77ed3c42fee219fb50bca154b1ae36dbca8fc2e0'/>
<id>urn:sha1:77ed3c42fee219fb50bca154b1ae36dbca8fc2e0</id>
<content type='text'>
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: cdce9xx: add support for cdce9xx clock synthesizer</title>
<updated>2019-10-11T17:32:39Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2019-09-27T16:14:26Z</published>
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<id>urn:sha1:260777fc2333183728d24fb0ffaa22a888c09655</id>
<content type='text'>
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>clk: versal: Add clock driver support</title>
<updated>2019-10-08T07:41:24Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2019-06-23T06:54:57Z</published>
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<id>urn:sha1:95105089afe2a204883e9c0f4c2c694469ec31d1</id>
<content type='text'>
This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>clk: add composite clk support</title>
<updated>2019-07-31T07:20:51Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2019-07-31T07:01:54Z</published>
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<id>urn:sha1:00097635888f9104da7f7cceaf1858ec8987e86f</id>
<content type='text'>
Import clk composite clk support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>clk: add clk-gate support</title>
<updated>2019-07-31T07:20:51Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2019-07-31T07:01:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1c643303187c595eb6782329529d2aec3731e473'/>
<id>urn:sha1:1c643303187c595eb6782329529d2aec3731e473</id>
<content type='text'>
Import clk-gate support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2019-07-27T13:35:05Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-07-27T13:35:05Z</published>
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<id>urn:sha1:df9a7a195bdf0722399199bf373afc8309ae3ad7</id>
<content type='text'>
u-boot-imx-20190719

- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
</content>
</entry>
<entry>
<title>clk: sandbox: Add sandbox test code for Common Clock Framework [CCF]</title>
<updated>2019-07-19T12:50:30Z</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2019-06-24T13:50:50Z</published>
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<id>urn:sha1:87e460c304ad6030bc2aab89edd44e433290d5bc</id>
<content type='text'>
This patch provides code to implement the CCF clock tree in sandbox. It
uses all the introduced primitives; some generic ones are reused, some
sandbox specific were developed.

In that way (after introducing the real CCF tree in sandbox) the recently
added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested
in their natural work environment.

Usage (sandbox_defconfig and sandbox_flattree_defconfig):
./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf"

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)</title>
<updated>2019-07-19T12:50:30Z</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2019-06-24T13:50:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1d7993d1d0efb7727de29ebbe164059b7bf71983'/>
<id>urn:sha1:1d7993d1d0efb7727de29ebbe164059b7bf71983</id>
<content type='text'>
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y
SHA1: 5752b50477da)to provide clocks support as it is used on the Linux
kernel with Common Clock Framework [CCF] setup.

The directory structure has been preserved. The ported code only supports
reading information from PLL, MUX, Divider, etc and enabling/disabling
the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic
to the alias numbering as the information about the clock is read from the
device tree.

One needs to pay attention to the comments indicating necessary for U-Boot's
driver model changes.

If needed, the code can be extended to support the "set" part of the clock
management.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: sifive: Factor-out PLL library as separate module</title>
<updated>2019-07-19T06:24:51Z</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-06-25T06:31:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d04c79d2b238e857c1b1f45a78d173152792b371'/>
<id>urn:sha1:d04c79d2b238e857c1b1f45a78d173152792b371</id>
<content type='text'>
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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