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<title>u-boot.git/drivers/clk/Makefile, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/Makefile?h=v2021.01</id>
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<updated>2020-09-30T15:55:23Z</updated>
<entry>
<title>clk: add clock driver for SCMI agents</title>
<updated>2020-09-30T15:55:23Z</updated>
<author>
<name>Etienne Carriere</name>
<email>etienne.carriere@linaro.org</email>
</author>
<published>2020-09-09T16:44:04Z</published>
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<id>urn:sha1:60388844836f5639e6c9a4331335ff22298128da</id>
<content type='text'>
This change introduces a clock driver for SCMI agent devices. When
SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a
clock device for each SCMI clock protocol devices enabled in the FDT.

SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled,
CONFIG_SCMI_AGENT is also enabled.

SCMI Clock protocol is defined in the SCMI specification [1].

Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi
Signed-off-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
Cc: Lukasz Majewski &lt;lukma@denx.de&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: clk_octeon: Add simple MIPS Octeon clock driver</title>
<updated>2020-08-03T19:11:41Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-07-30T11:56:16Z</published>
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<id>urn:sha1:b113c9b570a3d7ec654971b972ffb7b550139f75</id>
<content type='text'>
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC
family. Its for IO clock rate passing via DT in some of the Octeon
driver, like I2C. So that we don't need to use the non-mainline API
octeon_get_io_clock().

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>clk: Add K210 pll support</title>
<updated>2020-07-01T07:01:21Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-06-24T10:41:09Z</published>
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<id>urn:sha1:019ef9a3f32642abbf924931ecc9487300e74530</id>
<content type='text'>
This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
CC: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
</entry>
<entry>
<title>x86: Add a clock driver for Intel devices</title>
<updated>2020-02-07T14:41:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-06T16:54:53Z</published>
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<id>urn:sha1:b4d00b256e3c784de4a33a40f4cd28a94ee2a80c</id>
<content type='text'>
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.

This driver can be expanded later as needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: add clock driver for MediaTek MT76x8 platform</title>
<updated>2019-10-25T15:20:44Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2019-09-25T09:45:21Z</published>
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<id>urn:sha1:77ed3c42fee219fb50bca154b1ae36dbca8fc2e0</id>
<content type='text'>
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: cdce9xx: add support for cdce9xx clock synthesizer</title>
<updated>2019-10-11T17:32:39Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2019-09-27T16:14:26Z</published>
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<id>urn:sha1:260777fc2333183728d24fb0ffaa22a888c09655</id>
<content type='text'>
Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>clk: versal: Add clock driver support</title>
<updated>2019-10-08T07:41:24Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2019-06-23T06:54:57Z</published>
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<id>urn:sha1:95105089afe2a204883e9c0f4c2c694469ec31d1</id>
<content type='text'>
This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>clk: add composite clk support</title>
<updated>2019-07-31T07:20:51Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2019-07-31T07:01:54Z</published>
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<id>urn:sha1:00097635888f9104da7f7cceaf1858ec8987e86f</id>
<content type='text'>
Import clk composite clk support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>clk: add clk-gate support</title>
<updated>2019-07-31T07:20:51Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2019-07-31T07:01:34Z</published>
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<id>urn:sha1:1c643303187c595eb6782329529d2aec3731e473</id>
<content type='text'>
Import clk-gate support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20190719' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2019-07-27T13:35:05Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-07-27T13:35:05Z</published>
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<id>urn:sha1:df9a7a195bdf0722399199bf373afc8309ae3ad7</id>
<content type='text'>
u-boot-imx-20190719

- CCF for i.MX6
- nandbcb command to write SPL into NAND
- Switch to DM (i.MX28)
- Boards: Toradex, engicam, DH
- Fixes for i.MX8
- Fixes for i.MX7ULP

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/561147504
</content>
</entry>
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