u-boot.git/drivers/clk/Makefile, branch v2022.07

clk: nuvoton: Add support for NPCM750

2022-05-05T13:28:47Z

Add clock controller driver for NPCM750 Signed-off-by: Jim Liu Signed-off-by: Stanley Chu Reviewed-by: Sean Anderson

k210: use the board vendor name rather than the marketing name

2022-03-15T09:43:11Z

"kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal Signed-off-by: Niklas Cassel Reviewed-by: Leo Yu-Chi Liang

clk: Rename ICS8N3QV01 to CLK_ICS8N3QV01

2022-02-25T04:58:13Z

This driver was missing a clock prefix. Add one. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20211215163620.2770126-4-seanga2@gmail.com

clk: Alphabetize Makefile

2022-02-25T04:58:13Z

This alphabetizes the clock makefile by Kconfig option. This will help prevent merge conflicts. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20211215163620.2770126-2-seanga2@gmail.com

clk: clk_versaclock: Add support for versaclock driver

2021-08-21T22:23:02Z

The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford Reviewed-by: Sean Anderson

Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

2021-07-01T12:57:23Z

Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases

clk: zynq: Add clock wizard driver

2021-06-23T07:48:35Z

The Clocking Wizard IP supports clock circuits customized to your clocking requirements. The wizard support for dynamically reconfiguring the clocking primitives for Multiply, Divide, Phase Shift/Offset, or Duty Cycle. Limited by U-Boot clk uclass without set_phase API, this patch only provides set_rate to modify the frequency. Signed-off-by: Zhengxun Reviewed-by: Sean Anderson Signed-off-by: Michal Simek

clk: k210: Move k210 clock out of its own subdirectory

2021-06-17T01:40:58Z

Now that we have only one clock driver, we don't need to have our own subdirectory. Move the driver back with the rest of the clock drivers. The MAINTAINERS for kendryte pinctrl is also fixed since it has always been wrong. Signed-off-by: Sean Anderson Reviewed-by: Leo Yu-Chi Liang

clk: Add Microchip PolarFire SoC clock driver

2021-01-18T03:06:38Z

Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel Tested-by: Bin Meng

clk: move clk-ti-sci driver to 'ti' directory

2021-01-12T05:28:05Z

The patch moves the clk-ti-sci.c file to the 'ti' directory along with all the other TI's drivers, and renames it clk-sci.c. Signed-off-by: Dario Binacchi