<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/clk/altera/Makefile, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Replace TARGET namespace and cleanup properly</title>
<updated>2026-02-14T17:06:46+00:00</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@altera.com</email>
</author>
<published>2026-02-13T12:27:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=62f7a94602094617ac384839ed695c2906893a88'/>
<id>62f7a94602094617ac384839ed695c2906893a88</id>
<content type='text'>
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.

Signed-off-by: Brian Sune &lt;briansune@gmail.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;

# Conflicts:
#	drivers/ddr/altera/Makefile
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.

Signed-off-by: Brian Sune &lt;briansune@gmail.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;

# Conflicts:
#	drivers/ddr/altera/Makefile
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: altera: Add clock support for Agilex7 M-series</title>
<updated>2025-08-08T14:20:53+00:00</updated>
<author>
<name>Tingting Meng</name>
<email>tingting.meng@altera.com</email>
</author>
<published>2025-08-04T01:24:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7a7c10054d0af0f5973999240f266dce8425725d'/>
<id>7a7c10054d0af0f5973999240f266dce8425725d</id>
<content type='text'>
Agilex7 M-series reuse the clock driver from Agilex.

Signed-off-by: Tingting Meng &lt;tingting.meng@altera.com&gt;
Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Agilex7 M-series reuse the clock driver from Agilex.

Signed-off-by: Tingting Meng &lt;tingting.meng@altera.com&gt;
Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arch: arm: Agilex5 enablement</title>
<updated>2024-03-18T06:45:47+00:00</updated>
<author>
<name>Jit Loon Lim</name>
<email>jit.loon.lim@intel.com</email>
</author>
<published>2024-03-12T14:01:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=386fca68960994ece0d9da8a69a14495b5f1aedf'/>
<id>386fca68960994ece0d9da8a69a14495b5f1aedf</id>
<content type='text'>
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.

Signed-off-by: Jit Loon Lim &lt;jit.loon.lim@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.

Signed-off-by: Jit Loon Lim &lt;jit.loon.lim@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: clk: Add memory clock driver for Intel N5X device</title>
<updated>2021-08-25T04:55:13+00:00</updated>
<author>
<name>Siew Chin Lim</name>
<email>elly.siew.chin.lim@intel.com</email>
</author>
<published>2021-08-10T03:26:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=14b7fba31feea0ffbb6a2f5bf62ff1f9af59a90b'/>
<id>14b7fba31feea0ffbb6a2f5bf62ff1f9af59a90b</id>
<content type='text'>
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.

Signed-off-by: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.

Signed-off-by: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: clk: Add clock driver for Intel N5X device</title>
<updated>2021-08-25T04:51:53+00:00</updated>
<author>
<name>Siew Chin Lim</name>
<email>elly.siew.chin.lim@intel.com</email>
</author>
<published>2021-08-10T03:26:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05e1e3befa380c1f4114bfbd877b0b8ca334a5e9'/>
<id>05e1e3befa380c1f4114bfbd877b0b8ca334a5e9</id>
<content type='text'>
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.

Signed-off-by: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.

Signed-off-by: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: agilex: Add clock driver for Agilex</title>
<updated>2020-01-07T13:38:33+00:00</updated>
<author>
<name>Ley Foon Tan</name>
<email>ley.foon.tan@intel.com</email>
</author>
<published>2019-11-27T07:55:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c168fc71a32861a52a710015ee4a71e8cabe86d5'/>
<id>c168fc71a32861a52a710015ee4a71e8cabe86d5</id>
<content type='text'>
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang &lt;chee.hong.ang@intel.com&gt;
Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.

agilex-clock.h is from Linux commit ID cd2e1ad12247.

Signed-off-by: Chee Hong Ang &lt;chee.hong.ang@intel.com&gt;
Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: cosmetic: Convert SPDX license tags to Linux Kernel style</title>
<updated>2018-10-28T13:26:39+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2018-10-26T07:02:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=22929e1266e9a61048bfaef381ad4fb2e2fc3ef5'/>
<id>22929e1266e9a61048bfaef381ad4fb2e2fc3ef5</id>
<content type='text'>
Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: socfpga: Add initial Arria10 clock driver</title>
<updated>2018-08-13T20:35:42+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2018-07-31T15:58:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f9f016adcdc686bf3c50399492d579a024ed7520'/>
<id>f9f016adcdc686bf3c50399492d579a024ed7520</id>
<content type='text'>
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;chin.liang.see@intel.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;chin.liang.see@intel.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
