u-boot.git/drivers/clk/altera, branch next

drivers: clk: n5x: Add support for enable/disable API

2026-08-19T16:36:04Z

Update N5X clock driver to support enabling or disabling the peripheral clocks via clock driver model APIs. The caller will pass the clock ID to this driver and the driver will then proceed to manipulate the desired bit in the N5X clock manager peripheral PLL register based on the given clock ID. N5X_L4_SYS_FREE_CLK is a free-running clock with no gate control in hardware, therefore attempting to enable or disable it is not applicable. Return -EOPNOTSUPP for this clock ID and treat it as a no-op in socfpga_clk_enable() and socfpga_clk_disable(). Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Chen Huei Lok

drivers: clk: altera: arria10: Fix wrong API used for memory free

2026-08-19T16:36:03Z

Fix the wrong API used for memory free. Signed-off-by: Dinesh Maniyam

clk: altera: agilex: Update sync to async mode config in clk pll

2026-08-19T16:36:03Z

Remove MEMBUS_CLKSLICE_REG source synchronous mode configuration to run as source asynchronous mode. Switching the HPS PLL to async mode improves resistance to clock marginality issues such as F2S clk to HPS PLL Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Boon Khai Ng

clk: s10: Refactor S10 clock driver

2026-08-19T15:07:05Z

Refactor Stratix10 clock manager driver to support driver model, following Agilex clock driver. Create a new clock driver, clk-s10.c, for Stratix10 which supports the driver model. This allows several APIs such as enable/disable clock, and get clock rate to be supported. This driver will be initialized during SPL to bring up the clock as early as possible. The clock initialization process are refactored into this new driver from clock_manager_s10.c during clock driver probe. Excluding Stratix10 from legacy method of obtaining clkmgr base address in mach-socfpga/misc.c as the base address is already obtained during clock driver probe during SPL initialization. Signed-off-by: Alif Zakuan Yuslaimi

clk: altera: Use dev_read_addr_ptr()

2026-06-09T20:48:33Z

Replace devfdt_get_addr_ptr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan

Merge patch series "treewide: Clean up usage of DECLARE_GLOBAL_DATA_PTR"

2026-02-17T19:51:26Z

Peng Fan (OSS) says: This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR instances. Many files declare DECLARE_GLOBAL_DATA_PTR and include asm/global_data.h even though gd is never used. In these cases, asm/global_data.h is effectively treated as a proxy header, which is not a good practice. Following the Include What You Use principle, files should include only the headers they actually depend on, rather than relying on global_data.h indirectly. This approach is also adopted in Linux kernel [1]. The first few patches are prepartion to avoid building break after remove the including of global_data.h. A script is for filtering the files: list=`find . -name "*.[ch]"` for source in ${list} do result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}` if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then echo "Found in ${source}" result=`sed -n '/\/p' ${source}` result2=`sed -n '/\/p' ${source}` if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then echo "Cleanup ${source}" sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source} sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source} sed -i '/global_data.h/d' ${source} git add ${source} fi fi done [1] https://lpc.events/event/17/contributions/1620/attachments/1228/2520/Linux%20Kernel%20Header%20Optimization.pdf CI: https://github.com/u-boot/u-boot/pull/865 Link: https://lore.kernel.org/r/20260209-cleanup-v2-0-73a3a84ddbdb@nxp.com

treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage

2026-02-17T19:50:22Z

Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal #TI boards Acked-by: Yao Zi #TH1520 Signed-off-by: Peng Fan

Replace TARGET namespace and cleanup properly

2026-02-14T17:06:46Z

TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile

clk: altera: agilex: Exclude AGILEX_L4_SYS_FREE_CLK from enable/disable operations

2026-02-14T17:06:46Z

AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in hardware, therefore attempting to enable or disable it is not applicable. Update the clock driver to explicitly exclude this clock ID from enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id() and treating this as a no-op in the socfpga_clk_enable() and socfpga_clk_disable() functions. This prevents unnecessary register access for clocks that cannot be gated and ensures clean handling when the clock is present in the device tree. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

socfpga: agilex: fix NAND clock handling

2026-02-14T17:06:46Z

In v2025.10, the Agilex clock driver was updated to support clk_enable() and clk_disable() using clock-ID based bitmasks. However, only AGILEX_NAND_CLK was implemented, while the NAND DT node still referenced both nand and nand_x clocks. Since AGILEX_NAND_X_CLK is not defined in the clock driver or the clock-ID specification, clk_enable() failed during NAND probe. As a result, the Denali NAND controller never completed initialization. Fix this by mapping the NAND X clock to the existing l4_mp clock bitmask, aligning the DT expectations with the clock driver and restoring proper NAND controller initialization. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee