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<title>u-boot.git/drivers/clk/altera, branch v2022.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/altera?h=v2022.07</id>
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<updated>2022-07-01T07:00:39Z</updated>
<entry>
<title>drivers: clk: Update license for Intel N5X device</title>
<updated>2022-07-01T07:00:39Z</updated>
<author>
<name>Teik Heng Chong</name>
<email>teik.heng.chong@intel.com</email>
</author>
<published>2022-06-29T05:51:50Z</published>
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<id>urn:sha1:ef5ba2cef4a08b68caaa9215fcac142d3025bbf7</id>
<content type='text'>
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel,
update the license to use both GPL2.0 and BSD-3 Clause because this
copy of code may used for open source and internal project.

Signed-off-by: Teik Heng Chong &lt;teik.heng.chong@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>drivers: clk: Add memory clock driver for Intel N5X device</title>
<updated>2021-08-25T04:55:13Z</updated>
<author>
<name>Siew Chin Lim</name>
<email>elly.siew.chin.lim@intel.com</email>
</author>
<published>2021-08-10T03:26:32Z</published>
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<id>urn:sha1:14b7fba31feea0ffbb6a2f5bf62ff1f9af59a90b</id>
<content type='text'>
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.

Signed-off-by: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
</content>
</entry>
<entry>
<title>drivers: clk: Add clock driver for Intel N5X device</title>
<updated>2021-08-25T04:51:53Z</updated>
<author>
<name>Siew Chin Lim</name>
<email>elly.siew.chin.lim@intel.com</email>
</author>
<published>2021-08-10T03:26:30Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05e1e3befa380c1f4114bfbd877b0b8ca334a5e9'/>
<id>urn:sha1:05e1e3befa380c1f4114bfbd877b0b8ca334a5e9</id>
<content type='text'>
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.

Signed-off-by: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
</content>
</entry>
<entry>
<title>common: Drop asm/global_data.h from common header</title>
<updated>2021-02-02T20:33:42Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-10-31T03:38:53Z</published>
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<id>urn:sha1:401d1c4f5d2d29c4bc4beaec95402ca23eb63295</id>
<content type='text'>
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include &lt;asm/global_data.h&gt; at all, so
remove that include.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename ..._platdata variables to just ..._plat</title>
<updated>2020-12-13T23:51:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:23Z</published>
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<id>urn:sha1:8a8d24bdf174851ebb8607f359d54b72e3283b97</id>
<content type='text'>
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename ofdata_to_platdata() to of_to_plat()</title>
<updated>2020-12-13T23:51:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d1998a9fde0a917d6496299f6a97b6bccfdc6724'/>
<id>urn:sha1:d1998a9fde0a917d6496299f6a97b6bccfdc6724</id>
<content type='text'>
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata-&gt;plat rename.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename dev_get_platdata() to dev_get_plat()</title>
<updated>2020-12-13T23:51:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:20Z</published>
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<id>urn:sha1:c69cda25c9b59e53a6bc8969ada58942549f5b5d</id>
<content type='text'>
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename 'platdata' variables to just 'plat'</title>
<updated>2020-12-13T23:51:08Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:18Z</published>
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<id>urn:sha1:caa4daa2ae3dc0a3e516addea5772c9af76abcb0</id>
<content type='text'>
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: treewide: Rename auto_alloc_size members to be shorter</title>
<updated>2020-12-13T15:00:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-12-03T23:55:17Z</published>
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<id>urn:sha1:41575d8e4c334df148c4cdd7c40cc825dc0fcaa1</id>
<content type='text'>
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>clk: agilex: Additional membus writes for HPS PLL</title>
<updated>2020-10-09T09:53:10Z</updated>
<author>
<name>Chee Hong Ang</name>
<email>chee.hong.ang@intel.com</email>
</author>
<published>2020-07-10T12:55:23Z</published>
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<id>urn:sha1:d24f2bc1481323b37b056522b3b246ee2d59a943</id>
<content type='text'>
Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang &lt;chee.hong.ang@intel.com&gt;
Reviewed-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
</entry>
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