u-boot.git/drivers/clk/altera, branch v2025.07

drivers: clk: agilex5: Set PLL to asynchronous mode

2025-02-25T16:53:41Z

PLL frequency would overshoot from the original target in synchronous mode during low VCC voltage condition. To resolve this issue, PLL is set to run on asynchronous mode instead of enabling synchronous mode in the clock driver. Signed-off-by: Muhammad Hazim Izzat Zamri Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

drivers: clk: agilex5: Replace status polling with wait_for_bit_le32()

2025-02-25T16:53:37Z

Replace cm_wait_for_fsm() function with wait_for_bit_le32() function which supports accurate timeout. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Tien Fong Chee Reviewed-by: Tien Fong Chee

drivers: clk: agilex5: Configure intosc as boot_clk source

2025-02-25T16:53:35Z

Some customers prefer to minimize the use of external oscillators, especially when using the FPGA first configuration mode. By enabling the configuration of the HPS internal oscillator as the boot_clk source instead of the default external oscillator, (HPS_OSC_CLK) in non-secure boot scenarios, this allows them to eliminate the need for an additional oscillator device and a dedicated HPS pin, simplifying board layout and routing. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD

2024-10-11T17:44:48Z

Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass

Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"

2024-05-20T19:35:03Z

As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

clk: Remove and add needed includes

2024-05-07T14:00:41Z

Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini

global: Make include

2024-05-06T21:07:48Z

This follows the example of RISC-V where includes directly as "gd" includes a reference to bd_info already and so the first must include the second anyhow. We then remove from all of the places which include references to "gd" an so have already. Signed-off-by: Tom Rini

arch: arm: Agilex5 enablement

2024-03-18T06:45:47Z

This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim Reviewed-by: Tien Fong Chee

clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)

2024-01-22T08:51:17Z

MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation but it is wrongly defined as BIT[7] in u-boot code. This register is used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee