u-boot.git/drivers/clk/altera, branch v2026.04

drivers: clk: agilex: Use FIELD_GET during EMAC clock selection

2025-09-30T06:29:56Z

FIELD_GET() macro is used during EMAC clock source selection for better code readability and maintainability. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

drivers: clk: agilex: Fix EMAC clock source selection

2025-09-30T06:29:56Z

Fix the incorrect bit masking and bit shift used to compute EMAC control which in turn is used to select EMAC clock from EMAC source A or B. Signed-off-by: Naresh Kumar Ravulapalli Reviewed-by: Tien Fong Chee

drivers: clk: agilex: Support for enable/disable API

2025-09-30T06:29:55Z

Update Agilex clock driver to support enabling or disabling the peripheral clocks via clock driver model APIs. The caller will pass the clock ID to this driver and the driver will then proceed to manipulate the desired bit in the Agilex clock manager peripheral PLL register based on the given clock ID. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

clk: altera: Add clock support for Agilex7 M-series

2025-08-08T14:20:53Z

Agilex7 M-series reuse the clock driver from Agilex. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

drivers: clk: agilex: Replace status polling with wait_for_bit_le32()

2025-08-08T14:20:47Z

Replace cm_wait_for_fsm() function with wait_for_bit_le32() function which supports accurate timeout. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

drivers: clk: agilex: Use real clock source frequency

2025-08-08T08:00:16Z

Update the ARMv8 generic timer frequency register (cntfrq_el0) with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL). The generic timer frequency was set to 0x200000000 during boot clk which needs to be set to 0x400000000 when transition from boot clk to PLL clk. This will ensure that subsequent timer operations are based on the correct frequency, ensuring accurate timekeeping. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

clk: n5x: Fix misplaced paren

2025-07-30T09:45:29Z

Smatch reported an issue about the precedence of shift being higher than mask in clk_get_emac_clk_hz. This turned out to be a misplaced paren in one of the calculations. Fix this by placing the paren in the same place as in the other similar calculations in the same function. Signed-off-by: Andrew Goodbody

drivers: clk: agilex5: Set PLL to asynchronous mode

2025-02-25T16:53:41Z

PLL frequency would overshoot from the original target in synchronous mode during low VCC voltage condition. To resolve this issue, PLL is set to run on asynchronous mode instead of enabling synchronous mode in the clock driver. Signed-off-by: Muhammad Hazim Izzat Zamri Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee

drivers: clk: agilex5: Replace status polling with wait_for_bit_le32()

2025-02-25T16:53:37Z

Replace cm_wait_for_fsm() function with wait_for_bit_le32() function which supports accurate timeout. Signed-off-by: Alif Zakuan Yuslaimi Signed-off-by: Tien Fong Chee Reviewed-by: Tien Fong Chee

drivers: clk: agilex5: Configure intosc as boot_clk source

2025-02-25T16:53:35Z

Some customers prefer to minimize the use of external oscillators, especially when using the FPGA first configuration mode. By enabling the configuration of the HPS internal oscillator as the boot_clk source instead of the default external oscillator, (HPS_OSC_CLK) in non-secure boot scenarios, this allows them to eliminate the need for an additional oscillator device and a dedicated HPS pin, simplifying board layout and routing. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee