u-boot.git/drivers/clk/at91, branch master

clk: at91: Use dev_read_addr_ptr()

2026-06-09T20:48:33Z

Replace devfdt_get_addr_ptr() with dev_read_addr_ptr() when retrieving the register base address. dev_read_addr_ptr() supports both live device tree and flat DT backends, avoiding direct dependency on devfdt_* helpers. No functional changes. Signed-off-by: Peng Fan Tested-by: Manikandan Muralidharan

global: Correct duplicate U_BOOT_DRIVER entry names

2026-04-07T17:32:56Z

The U_BOOT_DRIVER macro creates a list of drivers used at link time, and all entries here must be unique. This in turn means that all entries in the code should also be unique in order to not lead to build failures later with unexpected build combinations. Typically, the problem we have here is when a driver is obviously based on another driver and didn't update this particular field and so while the name field reflects something unique the linker entry itself is not. In a few places this provides a more suitable string name as well, however. Reviewed-by: Marek Vasut Reviewed-by: Svyatoslav Ryhel # Tegra Reviewed-by: Peter Robinson Reviewed-by: Heiko Schocher Reviewed-by: Simon Glass Signed-off-by: Tom Rini

clk: Tighten some clock driver dependencies

2025-10-28T18:25:23Z

A few clock drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini

clk: at91: remove default values for PMC_PLL_ACR

2025-10-17T09:33:46Z

Remove default values for PMC PLL Analog Control Register(ACR) as the values are specific for each SoC and PLL, so load them from PLL characteristics structure Signed-off-by: Manikandan Muralidharan Signed-off-by: Varshini Rajendran

clk: at91: Add ACR in all PLL setting.

2025-10-17T09:32:28Z

Add ACR in all PLL setting. Add correct ACR value for each PLL used in different SoCs. Signed-off-by: Manikandan Muralidharan Signed-off-by: Varshini Rajendran

clk: at91: Fix use of unsigned loop index

2025-08-13T09:59:36Z

The use of the unsigned variable 'i' as a loop index leads to the test for i being non-negative always being true. Instead declare 'i' as an int so that the for loop will terminate as expected. If the original for loop completes 'i' will be 1 past the end of the array so decrement it in the subsequent error path to prevent an out of bounds access occurring. This issue was found by Smatch. Signed-off-by: Andrew Goodbody

clk: at91: Fix testing of unsigned variable to be negative

2025-08-13T09:59:36Z

The variable 'index' is declared as unsigned but used to receive the return value of a function returning 'int'. This value is then tested for being less than zero to detect an error condition but as index is unsigned this can never be true. Change the variable 'index' to be an int so that the error condition can be detected. This issue was found by Smatch. Signed-off-by: Andrew Goodbody

clk: at91: sama7d65: add clock support

2025-07-25T08:54:43Z

Add clock support for SAMA7D65 Signed-off-by: Ryan Wanner [romain.sioen@microchip.com: add Fractional PLL core output range] Signed-off-by: Romain Sioen [varshini.rajendran@microchip.com: adapt driver to upstream] Signed-off-by: Varshini Rajendran

clk: at91: Update MAX PLL and master clk ID

2025-07-25T08:54:43Z

Update the MAX PLL and master CLK ID to support sama7d65 SoC family. Signed-off-by: Ryan Wanner

clk: at91: sam9x7: add pmc driver for sam9x7 SoC family

2025-06-19T10:56:43Z

Add PMC driver support for sam9x7 SoC family Signed-off-by: Varshini Rajendran [balamanikandan.gunasundar@microchip.com: Add peripheral clock id for pmecc] Signed-off-by: Balamanikandan Gunasundar