u-boot.git/drivers/clk/at91, branch next

clk: Tighten some clock driver dependencies

2025-10-28T18:25:23+00:00

A few clock drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini

clk: at91: remove default values for PMC_PLL_ACR

2025-10-17T09:33:46+00:00

Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure

Signed-off-by: Manikandan Muralidharan 
Signed-off-by: Varshini Rajendran

clk: at91: Add ACR in all PLL setting.

2025-10-17T09:32:28+00:00

Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.

Signed-off-by: Manikandan Muralidharan 
Signed-off-by: Varshini Rajendran

clk: at91: Fix use of unsigned loop index

2025-08-13T09:59:36+00:00

The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody

clk: at91: Fix testing of unsigned variable to be negative

2025-08-13T09:59:36+00:00

The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody

clk: at91: sama7d65: add clock support

2025-07-25T08:54:43+00:00

Add clock support for SAMA7D65

Signed-off-by: Ryan Wanner 
[romain.sioen@microchip.com: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen 
[varshini.rajendran@microchip.com: adapt driver to upstream]
Signed-off-by: Varshini Rajendran

clk: at91: Update MAX PLL and master clk ID

2025-07-25T08:54:43+00:00

Update the MAX PLL and master CLK ID to support sama7d65
SoC family.

Signed-off-by: Ryan Wanner

clk: at91: sam9x7: add pmc driver for sam9x7 SoC family

2025-06-19T10:56:43+00:00

Add PMC driver support for sam9x7 SoC family

Signed-off-by: Varshini Rajendran 
[balamanikandan.gunasundar@microchip.com: Add peripheral clock id for pmecc]
Signed-off-by: Balamanikandan Gunasundar

clk: at91: clk-main: drop parent_name check when registering main_rc oscillator

2025-06-19T10:56:43+00:00

The clk_register function logs an error if parent_name is missing from the
Device Tree.On the SAM9X7, the main_rc node is omitted to stay aligned with
the Linux Device Tree.Remove the parent_name check in at91_clk_main_rc()
to allow it to pass NULL when the parent is not specified.

Signed-off-by: Manikandan Muralidharan

clk: at91: sam9x60-pll: add support for HW PLL freq dividers

2025-06-19T10:56:43+00:00

Add support for hardware dividers for PLL IDs.In sam9x7 SoC,
PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers
each.

fcorepllack -----> HW Div = 2 -+--> fpllack
                               |
                               +--> HW Div = 2 ---> fplladiv2ck

Signed-off-by: Varshini Rajendran