u-boot.git/drivers/clk/clk_versal.c, branch main

clk: versal: Fix out-of-bounds parent id for DUMMY_PARENT

2026-04-23T09:49:48Z

When a clock parent entry is DUMMY_PARENT (0xFFFFFFFE), masking it with CLK_PARENTS_ID_MASK (0xFFFF) produces the value 0xFFFE (65534). This value is stored in parent->id and later used as a clock array index in versal_clock_get_parentid(). Since clock_max_idx is typically 228, accessing clock[65534] is out-of-bounds, and the garbage value read is used as a clock ID in subsequent clock rate calculations, eventually causing U-Boot to crash. This is observed as a crash during "clk dump" on AMD Versal Gen 2. Fix this by setting parent->id = 0 for DUMMY_PARENT entries. Fixes: 95105089afe2 ("clk: versal: Add clock driver support") Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260327101053.900154-1-padmarao.begari@amd.com

clk: versal: Enable clock driver for Versal Gen 2

2025-12-19T07:25:26Z

Versal Gen 2 is using enhancement SMC format but in near future SCMI client should be used. This patch is just bridging this gap till SCMI server is fully tested. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e83c665408d1453a464dd02cd2a25bb0ed267131.1762788250.git.michal.simek@amd.com

clk: versal: Cleanup driver

2025-12-19T07:25:26Z

Remove unneeded debug messages, parenthesis and fix error message. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5b6fbcff1025415adc97e3e17eeb18863df4383e.1762778011.git.michal.simek@amd.com

clk: versal: Add support for CLK_AUTO_ID

2025-12-19T07:25:26Z

When CLK_AUTO_ID is enabled 8 higher bits of clk->id is unique clock identifier in clk uclass that's why it is necessary to mask lower bits which are clock ID. Also check that ID not bigger then maximum supported clock. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/647f1d2c7d274c1106558a655386ef92e0baf2c8.1762778011.git.michal.simek@amd.com

clk: versal: Use __data macro for moving variable to data section

2025-12-19T07:25:26Z

The commit 1b267fe1824e ("firmware: xilinx: Prepare code for new SMC firmware format") introduce new __data macro that's why use it in clock driver too. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/eac8d0ab60a018d6c59aa28c49691839a3eec174.1762511327.git.michal.simek@amd.com

drivers: firmware: update xilinx_pm_request to support max payload

2025-10-09T07:07:03Z

Currently xilinx_pm_request API supports four u32 payloads. However the legacy SMC format supports five u32 request payloads and extended SMC format supports six u32 request payloads. Add support for the same in xilinx_pm_request API. Also add two dummy arguments to all the callers of xilinx_pm_request. The TF-A always fills seven u32 return payload so add support for the same in xilinx_pm_request API. Signed-off-by: Naman Trivedi Signed-off-by: Venkatesh Yadav Abbarapu Acked-by: Senthil Nathan Thangaraj Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com

clk: xilinx: Separate legacy format to own handler

2025-10-09T07:07:03Z

It is a preparation for adding enhacement format support that's why there is a need to separate current support to own function. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/c4d546553d4f0d69ef75fb1132b7121f36dd306c.1756388537.git.michal.simek@amd.com

clk: xilinx: Call generic smc_call_handler()

2025-10-09T07:07:03Z

There is no reason to call SMC from clock driver directly when clock driver is a child of firmware driver which is providing it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d383d5fea680b33d2eddbca108c452cee97e98ea.1756388537.git.michal.simek@amd.com

clk: versal: Store driver data in data section

2025-03-03T15:09:59Z

Line 171 in README is describing that before relocation no code should use global variable because global variables are placed to BSS section which is initialized to 0 after relocation. On Versal platforms clock driver is initialized before relocation (via using dm,bootph-all flag in DT) and global variables are initialized which works if this is used only before relocation. But the variables are used after relocation too but values are zeroed which is ending up incorrect behavior. That's why place variables to data section to ensure that values are not cleared which is for now the quickest temporary solution. The correct way to do it is to move all global variables to private data to avoid it. Signed-off-by: Padmarao Begari Link: https://lore.kernel.org/r/20250218052419.1141139-1-padmarao.begari@amd.com Signed-off-by: Michal Simek

clk: versal: Update the reference clocks as per bindings

2025-03-03T12:29:57Z

As per the bindings the reference clocks naming has changed from "pl_alt_ref_clk" to "pl_alt_ref" and "ref_clk" to "ref". Update the same in the clock driver. Also add the fallback option for older DT bindings. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250206091533.1447234-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek