u-boot.git/drivers/clk/clk_zynq.c, branch master Unnamed repository; edit this file 'description' to name the repository. drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:48+00:00 371dc068bbf50c6ed6146c04ec83b644bcc79249 Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org> 
Use the new symbol to refer to any 'SPL' build, including TPL and VPL

Signed-off-by: Simon Glass <sjg@chromium.org>
Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" 2024-05-20T19:35:03+00:00 Tom Rini trini@konsulko.com 2024-05-20T19:35:03+00:00 03de305ec48b0bb28554372abb40ccd46dbe0bf9 As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> 
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" 2024-05-19T14:16:36+00:00 Tom Rini trini@konsulko.com 2024-05-19T02:20:43+00:00 d678a59d2d719da9e807495b4b021501f2836ca5 When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> 
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
clk: Remove <common.h> and add needed includes 2024-05-07T14:00:41+00:00 Tom Rini trini@konsulko.com 2024-05-02T01:30:36+00:00 92bb2cd42aee1d1bd3d7ff236e5874f3450d1a35 Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> 
Remove <common.h> from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
treewide: Remove clk_free 2024-01-30T03:35:02+00:00 Sean Anderson seanga2@gmail.com 2023-12-16T19:38:42+00:00 c9309f40a6831b1ac5cd0a7227b5c3717d34c812 This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com 
This function is a no-op. Remove it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
clk: treewide: switch to clock dump from clk_ops 2023-12-15T18:05:54+00:00 Igor Prusov ivprusov@sberdevices.ru 2023-11-09T10:55:15+00:00 bc3e313ff6af4b5cb09749185d0602a3d4b9b240 Switch to using new dump operation in clock provider drivers instead of overriding soc_clk_dump. Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru> Link: https://lore.kernel.org/r/20231109105516.24892-8-ivprusov@sberdevices.ru 
Switch to using new dump operation in clock provider drivers instead of
overriding soc_clk_dump.

Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-8-ivprusov@sberdevices.ru
clk: zynq: Move soc_clk_dump to Zynq clock driver 2023-12-15T17:33:09+00:00 Igor Prusov ivprusov@sberdevices.ru 2023-11-09T10:55:09+00:00 bdac755114111a4816c33c4a436ed49057245176 Move clock dump function in preparation for switching to dump function in clk_ops. Acked-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru> Link: https://lore.kernel.org/r/20231109105516.24892-2-ivprusov@sberdevices.ru 
Move clock dump function in preparation for switching to dump function
in clk_ops.

Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Igor Prusov <ivprusov@sberdevices.ru>
Link: https://lore.kernel.org/r/20231109105516.24892-2-ivprusov@sberdevices.ru
clk: Add clk_get_by_name_optional 2022-02-25T06:41:04+00:00 Sean Anderson seanga2@gmail.com 2022-01-15T20:52:47+00:00 e96e2132f977aab738994c11162b14695029be6e This adds a helper function for clk_get_by_name in cases where the clock is optional. Hopefully this helps point driver writers in the right direction. Also convert some existing users. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220115205247.566210-2-seanga2@gmail.com 
This adds a helper function for clk_get_by_name in cases where the clock is
optional. Hopefully this helps point driver writers in the right direction.
Also convert some existing users.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20220115205247.566210-2-seanga2@gmail.com
Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze 2021-02-23T15:45:55+00:00 Tom Rini trini@konsulko.com 2021-02-23T15:45:55+00:00 cbe607b920bc0827d8fe379ed4f5ae4e2058513e Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name 
Xilinx changes for v2021.04-rc3

qspi:
- Support for dual/quad mode
- Fix speed handling

clk:
- Add clock enable function for zynq/zynqmp/versal

gem:
- Enable clock for Versal
- Fix error path
- Fix mdio deregistration path

fpga:
- Fix buffer alignment for ZynqMP

xilinx:
- Fix reset reason clearing in ZynqMP
- Show silicon version in SPL for Zynq/ZynqMP
- Fix DTB selection for ZynqMP
- Rename zc1275 to zcu1275 to match DT name
clk: zynq: Add dummy clock enable function 2021-02-23T13:56:59+00:00 Michal Simek michal.simek@xilinx.com 2021-02-09T14:28:15+00:00 9b7aac75365b68bae2e8f7cf074ba95638d31882 A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>