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<title>u-boot.git/drivers/clk/exynos, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>clk: exynos: add support for Exynos7870 CMU</title>
<updated>2025-11-12T04:56:12+00:00</updated>
<author>
<name>Kaustabh Chakraborty</name>
<email>kauschluss@disroot.org</email>
</author>
<published>2025-10-17T15:21:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=67fea5775b37b53379434377691772602e3064b3'/>
<id>67fea5775b37b53379434377691772602e3064b3</id>
<content type='text'>
Introduce a simple clock driver for Exynos7870's CMU blocks, more
specifically, CMU_MIF, CMU_FSYS, and CMU_PERI banks. This should be
enough to serve U-Boot's minimal requirements.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
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<pre>
Introduce a simple clock driver for Exynos7870's CMU blocks, more
specifically, CMU_MIF, CMU_FSYS, and CMU_PERI banks. This should be
enough to serve U-Boot's minimal requirements.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: exynos: add function for Samsung CMU ops-&gt;request</title>
<updated>2025-11-12T04:56:12+00:00</updated>
<author>
<name>Kaustabh Chakraborty</name>
<email>kauschluss@disroot.org</email>
</author>
<published>2025-10-17T15:21:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4bee54fbfa9e5be4bb17435dc809b0002566f986'/>
<id>4bee54fbfa9e5be4bb17435dc809b0002566f986</id>
<content type='text'>
The request function performs a simple check if the clock with the
provided ID is present or not. This is done with a simple call to
clk_get_by_id(). A non-zero return value indicates that the requested
clock is not available.

In some cases, clk-&gt;dev points to the clock bank device instead of
the clock device. This pointer is therefore overwritten in order to
reference to the correct device instance.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
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<pre>
The request function performs a simple check if the clock with the
provided ID is present or not. This is done with a simple call to
clk_get_by_id(). A non-zero return value indicates that the requested
clock is not available.

In some cases, clk-&gt;dev points to the clock bank device instead of
the clock device. This pointer is therefore overwritten in order to
reference to the correct device instance.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: exynos: add support for PLL1417X</title>
<updated>2025-11-12T04:56:12+00:00</updated>
<author>
<name>Kaustabh Chakraborty</name>
<email>kauschluss@disroot.org</email>
</author>
<published>2025-10-17T15:21:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=526a257fdba7c1a8288b6454b1551a35b0ec5723'/>
<id>526a257fdba7c1a8288b6454b1551a35b0ec5723</id>
<content type='text'>
PLL1417X seem to be compatible with PLL0822X, as also seen in the
respective Linux kernel driver. Add an enum entry for the type, while
merely being an alias for PLL0822X.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
PLL1417X seem to be compatible with PLL0822X, as also seen in the
respective Linux kernel driver. Add an enum entry for the type, while
merely being an alias for PLL0822X.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: exynos: add support for fixed rate and fixed factor clocks</title>
<updated>2025-11-12T04:56:12+00:00</updated>
<author>
<name>Kaustabh Chakraborty</name>
<email>kauschluss@disroot.org</email>
</author>
<published>2025-10-17T15:21:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b006e40963c5db79fca7134cdfced643e095f64c'/>
<id>b006e40963c5db79fca7134cdfced643e095f64c</id>
<content type='text'>
Add register functions for fixed rate and fixed factor clock drivers.
The vendor-specific structs defined are borrowed from the CCF driver
found in the Linux kernel.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add register functions for fixed rate and fixed factor clock drivers.
The vendor-specific structs defined are borrowed from the CCF driver
found in the Linux kernel.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: exynos: provide device pointer to clk_register_* functions</title>
<updated>2025-11-12T04:56:12+00:00</updated>
<author>
<name>Kaustabh Chakraborty</name>
<email>kauschluss@disroot.org</email>
</author>
<published>2025-10-17T15:21:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2a07137641769e06d4775698ff05d3a63ce82743'/>
<id>2a07137641769e06d4775698ff05d3a63ce82743</id>
<content type='text'>
The device pointer set as NULL causes problems when clock banks depend
on clocks from another clock bank. In such case, the appropriate clock
needs to be resolved from OF phandle arguments, which is not possible if
the associated device is not provided. Make necessary changes to make
the correct device pointer available.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The device pointer set as NULL causes problems when clock banks depend
on clocks from another clock bank. In such case, the appropriate clock
needs to be resolved from OF phandle arguments, which is not possible if
the associated device is not provided. Make necessary changes to make
the correct device pointer available.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: exynos: Fix always true test</title>
<updated>2025-09-01T07:37:08+00:00</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-07-23T16:04:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c901732558fbee5b798bb7a065f7832d3a6bbc84'/>
<id>c901732558fbee5b798bb7a065f7832d3a6bbc84</id>
<content type='text'>
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>global: Rename SPL_TPL_ to PHASE_</title>
<updated>2024-10-11T17:44:48+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c10c8badf8233cac1593cd2bef4d0379ac9e5bd'/>
<id>5c10c8badf8233cac1593cd2bef4d0379ac9e5bd</id>
<content type='text'>
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use PHASE_ as the symbol to select a particular XPL build. This means
that SPL_TPL_ is no-longer set.

Update the comment in bootstage to refer to this symbol, instead of
SPL_

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: exynos: Add SSS clocks for Exynos850</title>
<updated>2024-07-24T07:37:09+00:00</updated>
<author>
<name>Sam Protsenko</name>
<email>semen.protsenko@linaro.org</email>
</author>
<published>2024-07-23T18:14:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=95d8937d7ceb191b99ed755998c42c9fbd263c82'/>
<id>95d8937d7ceb191b99ed755998c42c9fbd263c82</id>
<content type='text'>
Add ACLK (operating clock) and PCLK (bus clock) for Security Sub System
(SSS) in Exynos850. Those clocks are needed for RNG enablement.

Signed-off-by: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add ACLK (operating clock) and PCLK (bus clock) for Security Sub System
(SSS) in Exynos850. Those clocks are needed for RNG enablement.

Signed-off-by: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03de305ec48b0bb28554372abb40ccd46dbe0bf9'/>
<id>03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d678a59d2d719da9e807495b4b021501f2836ca5'/>
<id>d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
