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<title>u-boot.git/drivers/clk/mediatek, branch next</title>
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<updated>2026-08-13T16:35:20Z</updated>
<entry>
<title>clk: mediatek: mt8189: add missing qualifiers</title>
<updated>2026-08-13T16:35:20Z</updated>
<author>
<name>David Lechner</name>
<email>dlechner@baylibre.com</email>
</author>
<published>2026-07-31T19:25:02Z</published>
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<id>urn:sha1:4a6f93a28daee8a01fc0c9f797a653e64d97c046</id>
<content type='text'>
Add a missing const and a missing static qualifier to a couple of
lookup tables.

Reviewed-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260731-mtk-clk-mt8189-fix-missing-qualifiers-v1-1-92f3f0e44817@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt8188: fix top0 gate polarity</title>
<updated>2026-08-05T20:05:37Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-28T12:28:23Z</published>
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<id>urn:sha1:6a77840b2f01e98bbad157fd1984a2dce2a3eecd</id>
<content type='text'>
Gates in top0_cg_regs are active-high. The GATE_TOP0/GATE_TOP0E macros
set CLK_GATE_NO_SETCLR flags, which treat them as active-low. Enabling
the clock is currently disabling them.

Switch both macros to CLK_GATE_NO_SETCLR_INV to use the correct
active-high semantics.

Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Fixes: 11f3cc46322a ("clk: mediatek: add MT8188 clock driver")
Link: https://patch.msgid.link/20260728-mt8188-clk-fix-top0-gate-polarity-v1-1-56bc92ba6055@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: drop probe-after-bind provider setup</title>
<updated>2026-07-29T16:12:20Z</updated>
<author>
<name>David Lechner</name>
<email>dlechner@baylibre.com</email>
</author>
<published>2026-07-24T08:36:06Z</published>
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<id>urn:sha1:bf75f80082a194a95eb2aef039a746c5765ba8d1</id>
<content type='text'>
Parent lookup now probes the exact missing provider on demand, making the
eager probing of every parent provider after bind redundant. The common
bind callback also occupies a driver callback that a provider may need
for unrelated setup.

Remove the common bind callback and its use from all MediaTek parent
providers. Providers are now registered only when first needed or when
normal driver-model probing reaches them.

Signed-off-by: Carlo Caione &lt;ccaione@baylibre.com&gt;
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-2-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: probe parent providers on demand</title>
<updated>2026-07-29T16:06:00Z</updated>
<author>
<name>Carlo Caione</name>
<email>ccaione@baylibre.com</email>
</author>
<published>2026-07-24T08:36:05Z</published>
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<id>urn:sha1:976b12414c18cb7d601f073dcb2282bac1924197</id>
<content type='text'>
MediaTek clock trees can reference parents provided by a different clock
controller. The provider registry is populated when each controller
probes, so an early consumer can request a parent before its provider has
been registered.

When lookup misses, find the MediaTek clock device whose operations and
clock-tree type match the requested provider, then probe that device.
This removes the probe-order dependency without probing unrelated clock
controllers or treating a driver's bind callback as a type marker.

Co-developed-by: David Lechner &lt;dlechner@baylibre.com&gt;
Signed-off-by: Carlo Caione &lt;ccaione@baylibre.com&gt;
Link: https://patch.msgid.link/20260724-ccaione-upstream-fix-clk-probe-v2-1-ebcef2e94e9d@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt8188: add display related clock driver</title>
<updated>2026-07-29T15:47:02Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-15T15:24:26Z</published>
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<id>urn:sha1:9864f23f45a4b1f837dc873e670b7b00eefc4efc</id>
<content type='text'>
Add display related clock drivers, needed for HDMI support.

Signed-off-by: Chris-QJ Chen &lt;chris-qj.chen@mediatek.com&gt;
Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260715-mt8188-add-clk-add-display-related-clocks-v2-1-0aaf7accaeb0@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: get the clock tree from the driver data in mtk_common_clk_init</title>
<updated>2026-07-29T15:25:19Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-15T14:29:00Z</published>
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<id>urn:sha1:02ac5662ca6591beda139d8d01d5971a22ae13dc</id>
<content type='text'>
Every clock driver now stores its struct mtk_clk_tree in the compatible
data. Rename mtk_common_clk_init() to mtk_clk_probe() and make if fetch
the tree from dev_get_driver_data() instead of taking it as an argument,
so it matches the driver .probe prototype and can be used directly as
the probe callback.

Drop all the per-SoC probe wrappers that only forwarded the driver data
to mtk_clk_probe(), and point the corresponding drivers at
mtk_clk_probe() directly. The few controllers that still need a
dedicated probe for SoC specific register tweaks (some apmixedsys and
topckgen instances) keep it, but now call the single-argument
mtk_clk_probe().

This touches every MediaTek clock driver at once to keep the tree building
across the whole series.

No functional change intended.

Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-32-23e907516010@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt; (renamed mtk_common_clk_init() to mtk_clk_probe())
</content>
</entry>
<entry>
<title>clk: mediatek: remove the dedicated clock gate code path</title>
<updated>2026-07-29T15:25:19Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-15T14:28:59Z</published>
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<id>urn:sha1:c399402b0ebede2b68c47ea03d6301f96e4aa8c4</id>
<content type='text'>
Now that every MediaTek SoC describes its clock gates through struct
mtk_clk_tree and handles them with the generic topckgen ops, nothing uses
the dedicated clock gate code path anymore.

Remove struct mtk_cg_priv, the mtk_clk_gate_ops (of_xlate/enable/disable/
get_rate/dump) and mtk_common_clk_gate_init() from clk-mtk. Clock gate
controllers are now just regular mtk_clk_tree providers.

No functional change intended.

Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-31-23e907516010@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt8189: use driver data to store the clock tree</title>
<updated>2026-07-29T15:25:19Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-15T14:28:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0f9a65d7b0a72febff33e31da3a6975dd03faa44'/>
<id>urn:sha1:0f9a65d7b0a72febff33e31da3a6975dd03faa44</id>
<content type='text'>
Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8189 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys, topckgen and vlpckgen controllers keep their own
U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind()
callback, but they now get their tree from the compatible data, like the
clock gate controllers.

No functional change intended.

Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-30-23e907516010@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt8189: deduplicate clock gate drivers</title>
<updated>2026-07-29T15:24:37Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-15T14:28:57Z</published>
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<id>urn:sha1:6d0ba2669994e0a3efa35f444bd93506a9736477</id>
<content type='text'>
MT8189 already shares a single U_BOOT_DRIVER across all its clock gate
controllers, passing the per-controller gate table through the driver data
via a dedicated struct mt8189_gate_clk_data.

Now that struct mtk_clk_tree can describe the gates directly, drop that
bespoke helper: give each controller its own struct mtk_clk_tree
(.gates/.num_gates/.gates_offs) and use the generic mtk_clk_topckgen_ops.
The gate offset, previously computed at runtime from the first gate ID, is
now encoded statically in each tree.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-29-23e907516010@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt; (dropped _gates_offs arg from GATE_CLK_TREE)
</content>
</entry>
<entry>
<title>clk: mediatek: mt8512: use driver data to store the clock tree</title>
<updated>2026-07-29T15:10:10Z</updated>
<author>
<name>Julien Stephan</name>
<email>jstephan@baylibre.com</email>
</author>
<published>2026-07-15T14:28:56Z</published>
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<id>urn:sha1:02b947b367881233379ad1d3a608b7bb61a4af51</id>
<content type='text'>
Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8512 clock drivers, instead of a
dedicated probe per controller.

The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.

No functional change intended.

Signed-off-by: Julien Stephan &lt;jstephan@baylibre.com&gt;
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-28-23e907516010@baylibre.com
Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
</content>
</entry>
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