u-boot.git/drivers/clk/mediatek, branch v2019.04

clk: MediaTek: bind ethsys reset controller

2019-01-14T22:43:18Z

The ethsys contains not only the clock gating controller, but also the reset controller for the whole ethernet subsystem and its components. This patch adds binding of the reset controller so that the ethernet node can have references on it. Signed-off-by: Weijie Gao

clk: MediaTek: add clock driver for MT7623 SoC.

2018-11-29T04:04:51Z

This patch adds a driver for MT7623 clock blocks. Signed-off-by: Ryder Lee Tested-by: Matthias Brugger Reviewed-by: Simon Glass

clk: MediaTek: add clock driver for MT7629 SoC.

2018-11-29T04:04:51Z

This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: Ryder Lee Reviewed-by: Simon Glass