u-boot.git/drivers/clk/mediatek, branch v2020.07Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/mediatek?h=v2020.072020-05-19T01:19:23Zcommon: Drop linux/bitops.h from common header2020-05-19T01:19:23ZSimon Glasssjg@chromium.org2020-05-10T17:40:13Zurn:sha1:cd93d625fd751d55c729c78b10f82109d56a5f1d
Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
common: Drop linux/delay.h from common header2020-05-19T01:19:23ZSimon Glasssjg@chromium.org2020-05-10T17:40:11Zurn:sha1:c05ed00afb95fa5237f16962fccf5810437317bf
Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
common: Drop log.h from common header2020-05-19T01:19:18ZSimon Glasssjg@chromium.org2020-05-10T17:40:05Zurn:sha1:f7ae49fc4f363a803dab3be078e93ead8e75a8e9
Move this header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
clk: mediatek: use unsigned type for returning the clk rate2020-01-26T11:03:06ZFabien Parentfparent@baylibre.com2019-10-17T19:02:05Zurn:sha1:832685f07c75388e4f268d15536c988cc345b5a1
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
clk: mediatek: fix clock-rate overflow problem2020-01-16T14:39:45ZSam Shihsam.shih@mediatek.com2020-01-10T08:30:30Zurn:sha1:d8588ba55f84059ef43f6ad5b892df59543d0c41
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
clk: mediatek: add driver for MT76222020-01-16T14:39:45ZSam Shihsam.shih@mediatek.com2020-01-10T08:30:29Zurn:sha1:72ab603b201829be03eddef97f29169dcbfbe45d
This patch add clock driver for MediaTek MT7622 SoC.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
clk: mediatek: mt7629: add support for ssusbsys2020-01-16T14:39:45ZChunfeng Yunchunfeng.yun@mediatek.com2020-01-09T03:35:04Zurn:sha1:5f82a940a0379e32b3553bc0cd6d3ece2f8d0141
The SSUSB IP's clocks come from ssusbsys module on mt7629,
so add its driver
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll2020-01-16T14:39:45Zmingming leemingming.lee@mediatek.com2019-12-31T03:29:22Zurn:sha1:0670adb27aa99f87cc5f339efee0b9974711b026
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
clk: mediatek: add set_clr_upd mux type flow2020-01-16T14:39:45Zmingming leemingming.lee@mediatek.com2019-12-31T03:29:21Zurn:sha1:f62168d3c3d9bc0301dbc3ef9dc6d889ac19412e
Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
clk: mediatek: add driver support for MT85122020-01-16T14:39:45Zmingming leemingming.lee@mediatek.com2019-12-31T03:29:20Zurn:sha1:c196110777d0a62968f55421685451e4edb089d6
Add clock driver for MediaTek MT8512 SoC, include topckgen,
apmixedsys and infracfg support.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>