u-boot.git/drivers/clk/mediatek, branch v2020.10Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/mediatek?h=v2020.102020-08-24T18:11:31Zclk: mt7622: add needed clocks for ssusb-node2020-08-24T18:11:31ZFrank Wunderlichfrank-w@public-files.de2020-08-20T14:37:55Zurn:sha1:9f25aa13ea2f106885ea52a1039b9c6e7a677a35
MT7622 needs additional clock definitions to work properly
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
reset: drop unnecessary comment for pciesys2020-08-24T18:11:31ZFrank Wunderlichfrank-w@public-files.de2020-08-20T14:37:53Zurn:sha1:a300d696caee9e97da5a0b835451d27c98e07f8f
after review from sam this comment should be removed
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
reset: add basic reset controller for pciesys2020-08-19T21:38:15ZFrank Wunderlichfrank-w@public-files.de2020-08-13T08:20:46Zurn:sha1:fee276ee315ceff64900777b0b46cdafd88d1cfe
bind reset controller to pciesys
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
clk: mediatek: add pciesys support for MT7622 SoC2020-08-19T21:37:37ZChuanjia LiuChuanjia.Liu@mediatek.com2020-08-10T08:17:08Zurn:sha1:c5bfe694e7a0ca3ccb46001934acdabb0014eaf3
This patch adds pciesys support in clock driver for
MediaTek MT7622 SoC.
Signed-off-by: Henry Yen <henry.yen@mediatek.com>
Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
common: Drop linux/bitops.h from common header2020-05-19T01:19:23ZSimon Glasssjg@chromium.org2020-05-10T17:40:13Zurn:sha1:cd93d625fd751d55c729c78b10f82109d56a5f1d
Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
common: Drop linux/delay.h from common header2020-05-19T01:19:23ZSimon Glasssjg@chromium.org2020-05-10T17:40:11Zurn:sha1:c05ed00afb95fa5237f16962fccf5810437317bf
Move this uncommon header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
common: Drop log.h from common header2020-05-19T01:19:18ZSimon Glasssjg@chromium.org2020-05-10T17:40:05Zurn:sha1:f7ae49fc4f363a803dab3be078e93ead8e75a8e9
Move this header out of the common header.
Signed-off-by: Simon Glass <sjg@chromium.org>
clk: mediatek: use unsigned type for returning the clk rate2020-01-26T11:03:06ZFabien Parentfparent@baylibre.com2019-10-17T19:02:05Zurn:sha1:832685f07c75388e4f268d15536c988cc345b5a1
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate will become incorrect
because of the implicit cast between ulong -> int -> ulong.
This commit change the return type of mtk_clk_find_parent_rate to
ulong.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
clk: mediatek: fix clock-rate overflow problem2020-01-16T14:39:45ZSam Shihsam.shih@mediatek.com2020-01-10T08:30:30Zurn:sha1:d8588ba55f84059ef43f6ad5b892df59543d0c41
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
clk: mediatek: add driver for MT76222020-01-16T14:39:45ZSam Shihsam.shih@mediatek.com2020-01-10T08:30:29Zurn:sha1:72ab603b201829be03eddef97f29169dcbfbe45d
This patch add clock driver for MediaTek MT7622 SoC.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>