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<title>u-boot.git/drivers/clk/mediatek, branch v2024.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/mediatek?h=v2024.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/mediatek?h=v2024.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2024-05-19T14:16:36Z</updated>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d678a59d2d719da9e807495b4b021501f2836ca5'/>
<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>clk: Remove &lt;common.h&gt; and add needed includes</title>
<updated>2024-05-07T14:00:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-02T01:30:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=92bb2cd42aee1d1bd3d7ff236e5874f3450d1a35'/>
<id>urn:sha1:92bb2cd42aee1d1bd3d7ff236e5874f3450d1a35</id>
<content type='text'>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add clock driver support for MediaTek MT8365 SoC</title>
<updated>2023-12-19T15:09:06Z</updated>
<author>
<name>Julien Masson</name>
<email>jmasson@baylibre.com</email>
</author>
<published>2023-12-04T10:48:52Z</published>
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<id>urn:sha1:ac80c6a647229ba5058b5d979ca131d3b1a02bdd</id>
<content type='text'>
This patch adds clock driver support for MediaTek MT8365 SoC.
The changes are based on the Linux source code tag v6.7-rc2.

clk-mt8365.c has been written based on these kernel files:
- clk-mt8365.c (a96cbb146a9736f501fe66ebda6a9018735e5e8a)
- clk-mt8365-apmixedsys.c (65c9ad77cbc0eed78db94d80041aba675cfbdfa9)
And adapted following the clk attributes supported by U-Boot.

Signed-off-by: Julien Masson &lt;jmasson@baylibre.com&gt;
Reviewed-by: Mattijs Korpershoek &lt;mkorpershoek@baylibre.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add clock driver support for MediaTek MT7988 SoC</title>
<updated>2023-08-03T13:40:49Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2023-07-19T09:16:28Z</published>
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<id>urn:sha1:421436981a22c26b13b0afcaec4009a4fb82f405</id>
<content type='text'>
This patch adds clock driver support for MediaTek MT7988 SoC

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add clock driver support for MediaTek MT7981 SoC</title>
<updated>2022-09-23T19:09:16Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T12:00:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=40746bf429d22e28680290cb73afe60924efda1c'/>
<id>urn:sha1:40746bf429d22e28680290cb73afe60924efda1c</id>
<content type='text'>
This patch adds clock driver support for MediaTek MT7981 SoC

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add clock driver support for MediaTek MT7986 SoC</title>
<updated>2022-09-23T19:09:16Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T12:00:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=37d5a9a29dce9fba04e77e89373d3404c7fdb2ec'/>
<id>urn:sha1:37d5a9a29dce9fba04e77e89373d3404c7fdb2ec</id>
<content type='text'>
This patch adds clock driver support for MediaTek MT7986 SoC

Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add CLK_XTAL support for clock driver</title>
<updated>2022-09-23T19:09:16Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T12:00:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ad832b915a7f07e60eb58ed99bc36da5c3de8d42'/>
<id>urn:sha1:ad832b915a7f07e60eb58ed99bc36da5c3de8d42</id>
<content type='text'>
This adds the CLK_XTAL macro/flag to allow modeling clocks which are
directly connected to the xtal clock.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add infrasys clock mux support</title>
<updated>2022-09-23T19:09:16Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T12:00:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=570b0840b19a34ca6e42923c2cba0c8c64677e15'/>
<id>urn:sha1:570b0840b19a34ca6e42923c2cba0c8c64677e15</id>
<content type='text'>
This patch adds infrasys clock mux support for mediatek clock drivers.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add support to configure clock driver parent</title>
<updated>2022-09-23T19:09:16Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T12:00:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=98a8bbb9ea6de81407f338926e10cc1f743b9ba6'/>
<id>urn:sha1:98a8bbb9ea6de81407f338926e10cc1f743b9ba6</id>
<content type='text'>
This patch adds support for a clock node to configure its parent clock
where possible.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock</title>
<updated>2022-09-23T19:09:16Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-09-09T11:59:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7fb33e9aea514cfd873d8005954108a482e9e693'/>
<id>urn:sha1:7fb33e9aea514cfd873d8005954108a482e9e693</id>
<content type='text'>
The mtk clock framework in u-boot uses array index for searching clock
parent (kernel uses strings for search), so we need to specify a special
clock with ID=0 for CLK_XTAL in u-boot.

In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
expected.

However for newer chips, they may have some clocks with ID=0 not
representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
called. Current logic will make entire clock driver not working.

This patch adds a flag to indicate that whether a clock driver needs clocks
with ID=0 to call mtk_topckgen_get_mux_rate.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
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