<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/clk/mediatek, branch v2025.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/mediatek?h=v2025.01</id>
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<updated>2024-08-19T22:15:51Z</updated>
<entry>
<title>Merge patch series "clk: mediatek: mt7622: clk migration for OF_UPSTREAM"</title>
<updated>2024-08-19T22:15:51Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-08-19T22:15:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=aa2efb08732aa4daded61fca8e488eb211b28ce4'/>
<id>urn:sha1:aa2efb08732aa4daded61fca8e488eb211b28ce4</id>
<content type='text'>
Christian Marangi &lt;ansuelsmth@gmail.com&gt; says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock</title>
<updated>2024-08-19T22:15:26Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:25Z</published>
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<id>urn:sha1:105c78844a6cf72eefbfd614fc52da92bc0341f1</id>
<content type='text'>
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing clock PERI_UART4_PD</title>
<updated>2024-08-19T22:15:26Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:24Z</published>
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<id>urn:sha1:a776493f4b4b51515db456e635709a93e256dacd</id>
<content type='text'>
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing clock MUX1_SEL</title>
<updated>2024-08-19T22:15:26Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc'/>
<id>urn:sha1:a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc</id>
<content type='text'>
Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to
match the upstream clk ID order in preparation for OF_UPSTREAM.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing clock define for MAIN_CORE_EN</title>
<updated>2024-08-19T22:15:26Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6dfa991204a6fe033a5f0c49ff4f1d6e8af3ed7c'/>
<id>urn:sha1:6dfa991204a6fe033a5f0c49ff4f1d6e8af3ed7c</id>
<content type='text'>
Add missing clock for MAIN_CORE_EN. This is a special clock as it's a
gate for the APMIXED clocks required as a parent for CPU clocks.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: move INFRA_TRNG to the bottom</title>
<updated>2024-08-19T22:15:26Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=72461389583985a09b548b02f50fdfef817c621a'/>
<id>urn:sha1:72461389583985a09b548b02f50fdfef817c621a</id>
<content type='text'>
Move INFRA_TRNG clock to the bottom of the clk ID to match upstream
linux order. This is in preparation of OF_UPSTREAM.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: fix broken peri_cgs clk with XTAL parents</title>
<updated>2024-08-19T22:15:26Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c7978fd39568ef989fabd8ff6a5f0e6bfed06c7f'/>
<id>urn:sha1:c7978fd39568ef989fabd8ff6a5f0e6bfed06c7f</id>
<content type='text'>
Fix broken peri_cgs clock with XTAL parents as they have wrong
definition of the parent type.

Correctly fix them and use CLK_PARENT_XTAL for them.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "clk: mediatek: mt7986: clk migration for OF_UPSTREAM"</title>
<updated>2024-08-19T22:15:13Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-08-19T22:15:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f9e45be1a128e0b2d353a84a069eae1cb666309a'/>
<id>urn:sha1:f9e45be1a128e0b2d353a84a069eae1cb666309a</id>
<content type='text'>
Christian Marangi &lt;ansuelsmth@gmail.com&gt; says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
</content>
</entry>
<entry>
<title>clk: mediatek: mt7986: rename CK to CLK</title>
<updated>2024-08-19T22:14:44Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:40:48Z</published>
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<id>urn:sha1:54f8ba658fb43c9e74879807cd61f84188fdf697</id>
<content type='text'>
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: mt7986: convert to unified infracfg gates + muxes</title>
<updated>2024-08-19T22:14:44Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:40:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba7969c5fb12120d16ea9fee104468da833e5f86'/>
<id>urn:sha1:ba7969c5fb12120d16ea9fee104468da833e5f86</id>
<content type='text'>
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
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