u-boot.git/drivers/clk/mediatek, branch v2026.01

clk: mediatek: remove duplicate '@parent' field doc

2025-12-16T17:14:31Z

Remove duplicate '@parent' field documentation in struct mtk_composite. There is no need to say the same thing twice. Also fix spelling mistake in the word "parent" while we're at it. Signed-off-by: David Lechner

clk: mediatek: add dummy clk enable/disable ops for apmixedsys clocks

2025-05-22T19:55:05Z

Starting from commit ac30d90f336 (clk: Ensure the parent clocks are enabled while reparenting), MediaTek filogic platforms will crash on booting when initializing mmc devices. The root cause is that to simplify the code, we reused the topckgen ops for apmixedsys clocks as they share the get_rate with topckgen clocks while the clk enable/disable ops are not available for apmixedsys clocks. Now that a clock will be enabled first before reparenting, we have to add dummy enable/disable ops for apmixedsys to avoid unexpected behavior when apmixedsys clocks are the parent clock of the to-be-reparenting clocks. Fixes: 40746bf429d (clk: mediatek: add clock driver support for MediaTek MT7981 SoC) Fixes: 37d5a9a29dc (clk: mediatek: add clock driver support for MediaTek MT7986 SoC) Fixes: ece4e5804f5 (clk: mediatek: add clock driver support for MediaTek MT7987 SoC) Fixes: 421436981a2 (clk: mediatek: add clock driver support for MediaTek MT7988 SoC) Signed-off-by: Sam Shih Signed-off-by: Weijie Gao

arm: mediatek: remove CONFIG_MT8512

2025-02-21T17:36:37Z

Defining CONFIG_MT8512 is unnecessary as now board for mediatek target can be changed in config. Use CONFIG_TARGET_MT8512 to replace CONFIG_MT8512. Signed-off-by: Weijie Gao

clk: mediatek: add clock driver support for MediaTek MT7987 SoC

2025-01-30T20:35:14Z

This patch adds clock driver support for MediaTek MT7987 SoC Signed-off-by: Sam Shih Signed-off-by: Weijie Gao

clk: mediatek: fix uninitialized fields issue in INFRA_MUX struct

2025-01-23T18:11:49Z

This patch adds missing initialization of fields in INFRA_MUX struct which caused uart broken after any other infra mux being enabled by 'clk_prepare_enable' Signed-off-by: Sam Shih Signed-off-by: Weijie Gao

clk: mediatek: mt7629: fix gate offset of peri clock tree

2025-01-21T15:28:43Z

The clock definitions in mt7629-clk.h indicate that CLK_PERIBUS_SEL is the first element in the pericfg clock tree and also serves as a clock mux, unlike other clocks belonging to the clock gate in pericfg. This make the clock consumer get a wrong clock gate during request a clock from <&pericfg>. Since CLK_PERIBUS_SEL clock is not required in U-Boot, add a clock gate offset for the pericfg clock tree to resolve this problem. Signed-off-by: Sam Shih Signed-off-by: Weijie Gao

clk: mediatek: mt7629: fix parent clock of some top clock muxes

2024-12-31T16:58:52Z

According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL shares the same parent selection with CLK_TOP_IRRX_SEL, while the present parent selection for CLK_TOP_F10M_REF_SEL is actually used for CLK_TOP_SGMII_REF_1_SEL. Signed-off-by: Weijie Gao

Merge patch series "clk: mediatek: mt7622: clk migration for OF_UPSTREAM"

2024-08-19T22:15:51Z

Christian Marangi says: These are all the required patches to migrate clk and correctly support OF_UPSTREAM. This will align the clk index to upstream to support the same clk implementation with downstream and upstream DTS.

clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock

2024-08-19T22:15:26Z

Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also convert pericfg to mux + gate implementation as now we have also mux on top of gates. Signed-off-by: Christian Marangi

clk: mediatek: mt7622: add missing clock PERI_UART4_PD

2024-08-19T22:15:26Z

Add missing clock PERI_UART4_PD for peri clock gates. This is needed to match upstream linux clk ID in preparation for OF_UPSTREAM. Also convert infracfg to mux + gate implementation as now we have mux on top of gates. Signed-off-by: Christian Marangi