u-boot.git/drivers/clk/mediatek, branch v2026.04

clk: mediatek: mt7622: fix infracfg and pericfg clock operations

2026-03-17T18:51:45Z

The MT7622 infracfg and pericfg drivers both use mtk_common_clk_infrasys_init() for probe, which populates struct mtk_clk_priv and stores gate definitions in the clk_tree. However, both drivers were incorrectly wired to mtk_clk_gate_ops which expects struct mtk_cg_priv with separately populated gates/num_gates/gates_offs fields from mtk_common_clk_gate_init(). Since those fields were never set, any attempt to enable an infracfg or pericfg gate clock (e.g. CLK_INFRA_TRNG) would fail with -EINVAL. Switch both to mtk_clk_infrasys_ops and struct mtk_clk_priv to match the init function. Fixes: 72ab603b201 ("clk: mediatek: add driver for MT7622") Signed-off-by: Daniel Golle Reviewed-by: David Lechner Signed-off-by: David Lechner

clk: mtk: use IS_ERR_VALUE() to check rate return values

2026-01-21T19:30:58Z

Replace casting with long to IS_ERR_VALUE() macro to check for error return values from rate calculation functions. This is the recommended way to check the return value from clock rate functions. Signed-off-by: David Lechner

clk: mediatek: fix mux clocks with mapped parent IDs

2026-01-21T19:30:52Z

Pass the unmapped parent ID when setting parent for mux clocks. For technical reasons, some Mediatek clock driver have a mapping between the clock IDs used in the devicetree and ID used in the generic clock framework. The mtk_clk_mux_set_parent() function is comparing the passed mapped parent ID against the unmapped IDs in the chip-specific data structures. Before this change, we were passing the mapped parent ID. When there is a mapping, this resulted in buggy behavior (usually just incorrectly failing to find a match and returning an error). We need to pass the unmapped ID of the parent clock instead for the matching to work correctly. Since the reverse lookup is a bit verbose, a helper function is added to keep the code clean. Fixes: b1358915728b ("clk: mediatek: add of_xlate ops") Signed-off-by: David Lechner

clk: mediatek: mt8365: fix missing topckgen IDs

2026-01-12T19:35:03Z

Use a ID map to add clocks for the missing CLK_TOP_CLK32K and CLK_TOP_CLK26M that were not included in the devicetree definitions. This fixes getting the rate of any clock that had one of these as a parent. CLK_TOP_UNIVPLL does not appear to be a real clock, so it is omitted now since we can do that with the ID map as well. Signed-off-by: David Lechner

clk: mediatek: mt8365: remove separate topckgen-cg driver

2026-01-12T19:35:03Z

Remove the separate topckgen-cg driver for handling clock gates in the topckgen address space. The devicetree bindings for this were not acceptable upstream because it was creating a separate clock controller using the same address space as the main topckgen clock controller. The gates are moved to the topckgen tree instead. Signed-off-by: David Lechner

clk: mediatek: allow gates in topckgen drivers

2026-01-12T19:35:03Z

Add handling for gates in the topckgen clk drivers. This avoids the need to have separate topckgen-cg drivers and devicetree nodes for the same address space and clock ID range. Signed-off-by: David Lechner

clk: mediatek: mt8365: split struct mtk_clk_tree

2026-01-12T19:35:03Z

Split the struct mtk_clk_tree for MT8365 into separate structures for the apmixedsys, topckgen and infracfg clock controllers. This is needed to support moving the topckgen gates into the struct mtk_clk_tree. Since apmixedsys can also have gates, we need separate structures. Signed-off-by: David Lechner

clk: mediatek: mt8365: fix some clock parents

2026-01-12T19:35:03Z

Fix a number of clock parent definitions for MT8365 clocks. Most of these are just informational or don't make a function change. The clocks with the new PLL_FACTOR2 macro and the change in apu_parents are fixing actual bugs. Signed-off-by: David Lechner

clk: mediatek: fix fixed clock parents

2026-01-12T19:35:03Z

Add a flags field to struct mtk_fixed_clk to allow properly resolving the parent clock. All chip-specific clocks are updated to populate this field correctly. The parent is currently only used for printing debug information, so there are no functional bugs being fixed. Signed-off-by: David Lechner

clk: mediatek: add separate gates_offs for cg gates

2026-01-12T19:35:03Z

Add a gates_offs field to struct mtk_cg_priv and use that instead of struct mtk_clk_tree.gates_offs. Prior to this change, struct mtk_clk_tree.gates_offs could be the offset of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on the context. This was confusing and error-prone. For example, in mt8365 there is one set of gates that needs an offset and one that does not that share the same struct mtk_clk_tree. This is fixed in this patch by giving the correct offset for each gate separately. Signed-off-by: David Lechner