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<title>u-boot.git/drivers/clk/microchip/Kconfig, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>core: Rework REGMAP symbols implementation</title>
<updated>2026-03-30T22:59:35+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-03-17T01:24:19+00:00</published>
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As exposed by "make randconfig", we have an issue with the dependencies
for REGMAP (and xPL variants). As this is a library function, it should
always be selected and not depended on by other functionality. This is
largely done correctly today, so just correct the few outliers.

Acked-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
As exposed by "make randconfig", we have an issue with the dependencies
for REGMAP (and xPL variants). As this is a library function, it should
always be selected and not depended on by other functionality. This is
largely done correctly today, so just correct the few outliers.

Acked-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>clk: microchip: mpfs: support new syscon based devicetree configuration</title>
<updated>2024-10-29T11:58:22+00:00</updated>
<author>
<name>Conor Dooley</name>
<email>conor.dooley@microchip.com</email>
</author>
<published>2024-10-23T10:17:52+00:00</published>
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Why get a devicetree description wrong once when you can get it wrong
twice? The original mistake, which the driver supports was failing to
describe the main PLL that the "cfg" and "periph" clocks parented by.
The second mistake was describing the "cfg" and "periph" clocks a
reg region within the clock controller, rather as two registers within
a syscon region that also contains pinctrl, interrupt muxing controls
and other functions.

Make up for lost time and describe these regions as they should have
been originally, preserving support for the existing two configurations
for the sake of existing systems with firmware-provided devicetrees.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
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<pre>
Why get a devicetree description wrong once when you can get it wrong
twice? The original mistake, which the driver supports was failing to
describe the main PLL that the "cfg" and "periph" clocks parented by.
The second mistake was describing the "cfg" and "periph" clocks a
reg region within the clock controller, rather as two registers within
a syscon region that also contains pinctrl, interrupt muxing controls
and other functions.

Make up for lost time and describe these regions as they should have
been originally, preserving support for the existing two configurations
for the sake of existing systems with firmware-provided devicetrees.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>clk: Add Microchip PolarFire SoC clock driver</title>
<updated>2021-01-18T03:06:38+00:00</updated>
<author>
<name>Padmarao Begari</name>
<email>padmarao.begari@microchip.com</email>
</author>
<published>2021-01-15T02:50:38+00:00</published>
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<id>2f27c9219e45c8abcbd53b0e66eff1f5bcae7c7e</id>
<content type='text'>
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari &lt;padmarao.begari@microchip.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Tested-by: Bin Meng &lt;bin.meng@windriver.com&gt;
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<pre>
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari &lt;padmarao.begari@microchip.com&gt;
Reviewed-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Tested-by: Bin Meng &lt;bin.meng@windriver.com&gt;
</pre>
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