u-boot.git/drivers/clk/microchip, branch v2023.04

clk: microchip: mpfs: fix criticality of peripheral clocks

2022-11-15T07:37:17+00:00

Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari

clk: microchip: mpfs: fix periph clk parentage

2022-11-15T07:37:17+00:00

Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: microchip: mpfs: fix reference clock handling

2022-11-15T07:37:17+00:00

The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()

2022-11-15T07:37:17+00:00

Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.

Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.

Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.

The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.

Signed-off-by: Conor Dooley 
Reviewed-by: Leo Yu-Chi Liang 
Reviewed-by: Padmarao Begari

clk: Use generic CCF ops where possible

2022-03-30T18:18:56+00:00

This converts most CCF drivers to use generic ops. imx6q is the only
outlier, where we retain the existing functionality by moving the check to
request().

Signed-off-by: Sean Anderson 
Reviewed-by: Claudiu Beznea 
Reviewed-by: Peng Fan 
Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com
[ fixed missing include for at91 ]
Signed-off-by: Sean Anderson

doc: replace @return by Return:

2022-01-19T17:11:34+00:00

Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt

clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag

2021-04-08T07:37:30+00:00

This driver is needed in the pre-relocation phase as the serial
driver depends on it.

Signed-off-by: Bin Meng 
Reviewed-by: Padmarao Begari 
Tested-by: Padmarao Begari

clk: Add Microchip PolarFire SoC clock driver

2021-01-18T03:06:38+00:00

Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari 
Reviewed-by: Anup Patel 
Tested-by: Bin Meng