u-boot.git/drivers/clk/qcom/clock-qcom.h, branch master

clk/qcom: add initial clock driver for ipq5424

2025-06-23T16:50:21+00:00

Add initial set of clocks and resets for enabling U-Boot on ipq5424
based RDP platforms.

Signed-off-by: Varadarajan Narayanan 
Reviewed-by: Casey Connolly 
Link: https://lore.kernel.org/r/20250304110105.2762124-5-quic_varada@quicinc.com
Signed-off-by: Casey Connolly

clk: qcom: Allow polling for clock status in qcom_gate_clk_en()

2025-06-02T16:20:15+00:00

GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.

Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.

The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.

Reviewed-by: Neil Armstrong 
Signed-off-by: Stephan Gerhold 
Reviewed-by: Sumit Garg 
Reviewed-by: Casey Connolly 
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly

clk: qcom: Move qcom_gate_clk_en() to C file

2025-06-02T16:20:15+00:00

This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.

Reviewed-by: Neil Armstrong 
Signed-off-by: Stephan Gerhold 
Reviewed-by: Sumit Garg 
Reviewed-by: Casey Connolly 
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly

clk/qcom: bubble up qcom_gate_clk_en() errors

2025-03-17T15:12:15+00:00

If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.

Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.

Reviewed-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly

clk/qcom: add initial clock driver for ipq9574

2025-03-17T13:38:17+00:00

Add initial set of clocks and resets for enabling U-Boot on ipq9574
based RDP platforms.

Reviewed-by: Caleb Connolly 
Signed-off-by: Varadarajan Narayanan 
Link: https://lore.kernel.org/r/20250226064505.1178054-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly

clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock

2025-01-22T15:36:15+00:00

The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.

Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.

Signed-off-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly

clk/qcom: implement clk dump

2024-10-04T12:57:03+00:00

Add support for dumping a few of the clocks used on Qualcomm platforms.
Naming the Global PLL's, Root Clock Generators, and gate clocks.

This helps a lot with platform bringup and feature enablement by making
it easy to sanity check that the clocks are programmed correctly.

== Usage ==

Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of
qcom-.c.

The "clk dump" command should print the states of all the gates, GPLLs
and RCGs for your SoC.

== Glossary ==

RCG: Root Clock Generator
* Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
* Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with
support for .5 offsets).

GPLL: Global Phase Locked Loop
* Crystal as input
* integer multiplier + exponent part (2^-40)

Gate: Simple on/off clock
* Put between RCGs and the peripherals they power
* Required to allow for correct power sequencing

If you do the maths manually using the equations from "clk dump", the
numbers should roughly line up by they're likely to be out by a handful
of MHz. They output is formatted so that it can be pasted directly into
the python interpreter.

Signed-off-by: Caleb Connolly

clk/qcom: add initial clock driver for sc7280

2024-09-06T08:47:46+00:00

We don't actually need any clocks to get UFS up and running, resets are
useful though.

Reviewed-by: Neil Armstrong 
Reviewed-by: Simon Glass 
Signed-off-by: Caleb Connolly

clk/qcom: sdm845: enable SDCC2 core clock

2024-04-23T11:29:08+00:00

Allow setting the clock rate for the SD card core clock. This is
required for SD card support on SDM845 devices.

Signed-off-by: Caleb Connolly

clk/qcom: add driver for sm8250 GCC

2024-04-23T11:29:05+00:00

Add a clock driver for the SM8250 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.

Signed-off-by: Caleb Connolly