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<title>u-boot.git/drivers/clk/qcom/clock-sa8775p.c, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/qcom/clock-sa8775p.c?h=main</id>
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<updated>2026-05-18T09:04:13Z</updated>
<entry>
<title>clk: qcom: sa8775p: Add UFS clock support</title>
<updated>2026-05-18T09:04:13Z</updated>
<author>
<name>Balaji Selvanathan</name>
<email>balaji.selvanathan@oss.qualcomm.com</email>
</author>
<published>2026-04-27T09:26:07Z</published>
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<id>urn:sha1:4b1580e060847ce63b38a1f87bd482b60ec6523f</id>
<content type='text'>
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Signed-off-by: Balaji Selvanathan &lt;balaji.selvanathan@oss.qualcomm.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: sa8775p: Fix USB clock configuration and add resets</title>
<updated>2026-01-14T15:25:09Z</updated>
<author>
<name>Balaji Selvanathan</name>
<email>balaji.selvanathan@oss.qualcomm.com</email>
</author>
<published>2026-01-13T06:58:55Z</published>
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<id>urn:sha1:f4886799a0afd20ab4df663247bff3c1a78a2b85</id>
<content type='text'>
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")

Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.

Signed-off-by: Balaji Selvanathan &lt;balaji.selvanathan@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com
[casey: indentation fix]
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: sa8775p: Add QUP serial engine clock support</title>
<updated>2026-01-14T15:25:09Z</updated>
<author>
<name>Swathi Tamilselvan</name>
<email>swathi.tamilselvan@oss.qualcomm.com</email>
</author>
<published>2026-01-13T04:22:13Z</published>
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<id>urn:sha1:3422e915aca58faf32a80eaa3a05e7894307f81c</id>
<content type='text'>
Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.

This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.

Signed-off-by: Swathi Tamilselvan &lt;swathi.tamilselvan@oss.qualcomm.com&gt;
Signed-off-by: Balaji Selvanathan &lt;balaji.selvanathan@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260113042213.3107106-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk/qcom: bubble up qcom_gate_clk_en() errors</title>
<updated>2025-03-17T15:12:15Z</updated>
<author>
<name>Caleb Connolly</name>
<email>caleb.connolly@linaro.org</email>
</author>
<published>2025-03-14T15:31:19Z</published>
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<id>urn:sha1:7c5460afec3fd71c940a5e1a977655a267795f75</id>
<content type='text'>
If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.

Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.

Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk/qcom: add initial clock driver for qcs9100</title>
<updated>2025-01-22T15:26:51Z</updated>
<author>
<name>Varadarajan Narayanan</name>
<email>quic_varada@quicinc.com</email>
</author>
<published>2025-01-10T05:08:14Z</published>
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<id>urn:sha1:b3c48d8f827805fdbf0df8c07b5d24f05a3ec081</id>
<content type='text'>
Add initial set of clocks and resets for enabling U-Boot on QCS9100
based Ride platforms.

Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Signed-off-by: Varadarajan Narayanan &lt;quic_varada@quicinc.com&gt;
Link: https://lore.kernel.org/r/20250110050817.3819282-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</content>
</entry>
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