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<title>u-boot.git/drivers/clk/qcom, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/qcom?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/clk/qcom?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2026-07-07T00:26:12Z</updated>
<entry>
<title>Merge branch 'next'</title>
<updated>2026-07-07T00:26:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-07-07T00:26:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ee5d46b45ec0c63f8f9dd1e816e0dac3452ccc3d'/>
<id>urn:sha1:ee5d46b45ec0c63f8f9dd1e816e0dac3452ccc3d</id>
<content type='text'>
</content>
</entry>
<entry>
<title>clk/qcom: milos: Add TCSRCC clocks</title>
<updated>2026-06-30T11:04:59Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2026-06-25T13:14:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e4f83e403ad4f7b6c08ee83378e4887aaa153b1a'/>
<id>urn:sha1:e4f83e403ad4f7b6c08ee83378e4887aaa153b1a</id>
<content type='text'>
With a recent change to the UFS driver, now all clocks need to be
available. Add all the clocks from the TCSRCC block on Milos.

Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260625-milos-ufs-fix-v1-2-b0923dabc35f@fairphone.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk/qcom: milos: Add remaining UFS clocks</title>
<updated>2026-06-30T11:04:59Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2026-06-25T13:14:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c7ff1b5407199d94ac6ecb5c939ad07cb83e846'/>
<id>urn:sha1:5c7ff1b5407199d94ac6ecb5c939ad07cb83e846</id>
<content type='text'>
With a recent change to the UFS driver, now all clocks need to be
available. Add them.

Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260625-milos-ufs-fix-v1-1-b0923dabc35f@fairphone.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk/qcom: qcm2290: Fix vote_bit of gpll6 clock</title>
<updated>2026-05-18T09:06:02Z</updated>
<author>
<name>Biswapriyo Nath</name>
<email>nathbappai@gmail.com</email>
</author>
<published>2026-05-15T18:10:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bf6de8136737c4362a442d810deeadadab3d7948'/>
<id>urn:sha1:bf6de8136737c4362a442d810deeadadab3d7948</id>
<content type='text'>
This changes the vote_bit same as enable_mask in Linux clock driver.

Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table")
Signed-off-by: Biswapriyo Nath &lt;nathbappai@gmail.com&gt;
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk/qcom: Add SM6125 clock driver</title>
<updated>2026-05-18T09:04:14Z</updated>
<author>
<name>Biswapriyo Nath</name>
<email>nathbappai@gmail.com</email>
</author>
<published>2026-02-04T16:10:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=140f248556f48e595480e207af13aa48629566a3'/>
<id>urn:sha1:140f248556f48e595480e207af13aa48629566a3</id>
<content type='text'>
Add clock driver for the GCC block found in the SM6125 SoC.

Signed-off-by: Biswapriyo Nath &lt;nathbappai@gmail.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: sc7280: Add UFS clock support</title>
<updated>2026-05-18T09:04:13Z</updated>
<author>
<name>Balaji Selvanathan</name>
<email>balaji.selvanathan@oss.qualcomm.com</email>
</author>
<published>2026-04-27T09:26:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7e670b7d6e10e5e072dfe05f425e635acec2524c'/>
<id>urn:sha1:7e670b7d6e10e5e072dfe05f425e635acec2524c</id>
<content type='text'>
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Signed-off-by: Balaji Selvanathan &lt;balaji.selvanathan@oss.qualcomm.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: qcs615: Add UFS clock support</title>
<updated>2026-05-18T09:04:13Z</updated>
<author>
<name>Balaji Selvanathan</name>
<email>balaji.selvanathan@oss.qualcomm.com</email>
</author>
<published>2026-04-27T09:26:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=213edfd64501fca1c9e62640b4b1b362a2fd486a'/>
<id>urn:sha1:213edfd64501fca1c9e62640b4b1b362a2fd486a</id>
<content type='text'>
Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Signed-off-by: Balaji Selvanathan &lt;balaji.selvanathan@oss.qualcomm.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: sa8775p: Add UFS clock support</title>
<updated>2026-05-18T09:04:13Z</updated>
<author>
<name>Balaji Selvanathan</name>
<email>balaji.selvanathan@oss.qualcomm.com</email>
</author>
<published>2026-04-27T09:26:07Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4b1580e060847ce63b38a1f87bd482b60ec6523f'/>
<id>urn:sha1:4b1580e060847ce63b38a1f87bd482b60ec6523f</id>
<content type='text'>
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Signed-off-by: Balaji Selvanathan &lt;balaji.selvanathan@oss.qualcomm.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk/qcom: Add Milos clock driver</title>
<updated>2026-04-27T10:38:44Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2026-03-18T12:46:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0661dc33050886f169192723feb301c8cee00a79'/>
<id>urn:sha1:0661dc33050886f169192723feb301c8cee00a79</id>
<content type='text'>
Add Clock driver for the GCC block found in the Milos SoC.

The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref"
clock), so we need to pass that as well.

Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Reviewed-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: sc7280: add missing SDCC1 clocks</title>
<updated>2026-04-27T10:38:44Z</updated>
<author>
<name>Ajit Singh</name>
<email>blfizzyy@gmail.com</email>
</author>
<published>2026-02-26T19:32:17Z</published>
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<id>urn:sha1:16a16b55ce5fd75097bc07e7c0503b59b5401a81</id>
<content type='text'>
Add GCC_SDCC1_AHB_CLK and GCC_SDCC1_APPS_CLK gate clocks.
Required on platforms where SDCC1 is used for eMMC.

Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=a3cc092196ef63570c8744c3ac88c3c6c67ab44b

Signed-off-by: Ajit Singh &lt;blfizzyy@gmail.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Reviewed-by: Sumit Garg &lt;sumit.garg@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260226193217.82657-1-blfizzyy@gmail.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
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