u-boot.git/drivers/clk/qcom, branch next Unnamed repository; edit this file 'description' to name the repository. clk: qcom: sa8775p: Fix USB clock configuration and add resets 2026-01-14T15:25:09+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2026-01-13T06:58:55+00:00 f4886799a0afd20ab4df663247bff3c1a78a2b85 Correct USB30 primary clock RCG configuration and add missing USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration. Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition. Extend reset map with USB-related BCR entries and video BCR for comprehensive reset control support. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com [casey: indentation fix] Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")

Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com
[casey: indentation fix]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: sa8775p: Add QUP serial engine clock support 2026-01-14T15:25:09+00:00 Swathi Tamilselvan swathi.tamilselvan@oss.qualcomm.com 2026-01-13T04:22:13+00:00 3422e915aca58faf32a80eaa3a05e7894307f81c Add clock gate definitions and entries for QUP (Qualcomm Universal Peripheral) serial engine clocks across all four wrappers on SA8775P. This enables proper clock management for I2C, SPI, and UART peripherals connected to the QUP blocks. This resolves the "unknown clock ID 133" error for UART10 and provides complete QUP clock infrastructure for the platform. Signed-off-by: Swathi Tamilselvan <swathi.tamilselvan@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Link: https://patch.msgid.link/20260113042213.3107106-1-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.

This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.

Signed-off-by: Swathi Tamilselvan <swathi.tamilselvan@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260113042213.3107106-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk/qcom: sc7280: add more QUP clocks 2026-01-14T15:25:09+00:00 Casey Connolly casey.connolly@linaro.org 2026-01-08T19:49:55+00:00 142df62cb68dae574632640682b9e035ff076720 Add more clocks for UART2, i2c9 and a few others. This is enough to get the rubikpi 3 working. Link: https://patch.msgid.link/20260108195007.3156604-1-casey.connolly@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.

Link: https://patch.msgid.link/20260108195007.3156604-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk/qcom: qcm2290: Add SDCC1 apps clock frequency table 2026-01-14T15:25:09+00:00 Loic Poulain loic.poulain@oss.qualcomm.com 2025-12-10T15:54:53+00:00 3ddc67573fab30fb4805cb6b2d44eff5386c84df Add support for configuring the SDCC1 apps clock on QCM2290 by introducing a frequency table and enabling dynamic rate setting. Previously, the clock was assumed to be fixed at 384 MHz by firmware, which limited flexibility and correctness when selecting optimal rates for SD/MMC operations. Suggested-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://patch.msgid.link/20251210155454.1561611-2-loic.poulain@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.

Suggested-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20251210155454.1561611-2-loic.poulain@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk/qcom: sc7280: add uart5 and uart7 clocks 2025-10-30T17:04:51+00:00 Casey Connolly casey.connolly@linaro.org 2025-07-14T13:13:16+00:00 9887944c4fa44cab668626b8e9d07a18f41e4246 Allow us to power up UART7 so we can load the QUP firmware, this is used for bluetooth on RB3 Gen 2 and possibly other boards. Additionally add the UART5 clocks so we can adjust baud rate for UART Signed-off-by: Casey Connolly <casey.connolly@linaro.org> Link: https://patch.msgid.link/20250714-geni-load-fw-v5-5-5abbc0d29838@linaro.org Signed-off-by: Casey Connolly <kcxt@postmarketos.org> 
Allow us to power up UART7 so we can load the QUP firmware, this is used
for bluetooth on RB3 Gen 2 and possibly other boards.

Additionally add the UART5 clocks so we can adjust baud rate for UART

Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20250714-geni-load-fw-v5-5-5abbc0d29838@linaro.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
clk/qcom: add driver for SM7150 GCC 2025-10-29T11:27:33+00:00 Danila Tikhonov danila@jiaxyga.com 2025-08-31T00:45:59+00:00 834cbecce790a6b8abb4869a7c416cf8b7ecaa51 Add a clock driver for the SM7150 SoC. This driver can enable necessary clocks for UART, UFS, USB, and MMC. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Co-developed-by: Jens Reidel <adrian@mainlining.org> Signed-off-by: Jens Reidel <adrian@mainlining.org> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250831004602.699953-2-adrian@mainlining.org Signed-off-by: Casey Connolly <kcxt@postmarketos.org> 
Add a clock driver for the SM7150 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Co-developed-by: Jens Reidel <adrian@mainlining.org>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250831004602.699953-2-adrian@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
clk/qcom: Add SM6350 clock driver 2025-10-29T11:27:33+00:00 Luca Weiss luca.weiss@fairphone.com 2025-09-17T12:47:34+00:00 4bae5827928c3f731c34e36589061f3d2f9c1159 Add Clock driver for the GCC block found in the SM6350 SoC. Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> 
Add Clock driver for the GCC block found in the SM6350 SoC.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
clk/qcom: sm8250: Remove unused defines 2025-10-29T11:27:33+00:00 Luca Weiss luca.weiss@fairphone.com 2025-09-24T11:30:08+00:00 43a2fc67d3830fd2bc9e0736605b2d324eaa4f3c Clean up some defines which are not used in the driver. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-2-7e75842ca714@fairphone.com Signed-off-by: Casey Connolly <kcxt@postmarketos.org> 
Clean up some defines which are not used in the driver.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-2-7e75842ca714@fairphone.com
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
clk/qcom: sdm845: add support for sdm670 2025-10-29T11:27:32+00:00 David Wronek david.wronek@mainlining.org 2025-10-03T10:01:10+00:00 8111e1357e6dd1537f4bb1b00721e0356009d89f The global clock controller on SDM670 is similar to SDM845, so let's add support here. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: David Wronek <david.wronek@mainlining.org> Link: https://lore.kernel.org/r/20251003-sdm670-v2-2-52c0fa481286@mainlining.org Signed-off-by: Casey Connolly <kcxt@postmarketos.org> 
The global clock controller on SDM670 is similar to SDM845, so let's add
support here.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-2-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
clk: qcom: sm8650: add usb3 noc clk 2025-07-14T13:35:24+00:00 Rui Miguel Silva rui.silva@linaro.org 2025-06-18T09:32:16+00:00 07ddbb89c9cc42a366807813dcb28fbd3e9d198b Commit [0] introduced, correctly, the bubble of qcom clock errors to make it easy to spot missing clocks in the platforms, and this is a case of that, add the GCC_CFG_NOC_USB3_PRIM_AXI_CLK clock to sm8650 clock pool. 0: 7c5460afec3f ("clk/qcom: bubble up qcom_gate_clk_en() errors") Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250618093253.225929-1-rui.silva@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Commit [0] introduced, correctly, the bubble of qcom clock errors to
make it easy to spot missing clocks in the platforms, and this is a case
of that, add the GCC_CFG_NOC_USB3_PRIM_AXI_CLK clock to sm8650 clock
pool.

0: 7c5460afec3f ("clk/qcom: bubble up qcom_gate_clk_en() errors")

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250618093253.225929-1-rui.silva@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>