u-boot.git/drivers/clk/qcom, branch next Unnamed repository; edit this file 'description' to name the repository. clk/qcom: qcm2290: Fix vote_bit of gpll6 clock 2026-05-18T09:06:02+00:00 Biswapriyo Nath nathbappai@gmail.com 2026-05-15T18:10:03+00:00 bf6de8136737c4362a442d810deeadadab3d7948 This changes the vote_bit same as enable_mask in Linux clock driver. Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table") Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
This changes the vote_bit same as enable_mask in Linux clock driver.

Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table")
Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk/qcom: Add SM6125 clock driver 2026-05-18T09:04:14+00:00 Biswapriyo Nath nathbappai@gmail.com 2026-02-04T16:10:52+00:00 140f248556f48e595480e207af13aa48629566a3 Add clock driver for the GCC block found in the SM6125 SoC. Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> soc98: input: 1 [x] mmc@4784000.cd-gpios soc98: input: 0 [x] mmc@4784000.cd-gpios Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add clock driver for the GCC block found in the SM6125 SoC.

Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
soc98: input: 1 [x] mmc@4784000.cd-gpios
soc98: input: 0 [x] mmc@4784000.cd-gpios
Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: sc7280: Add UFS clock support 2026-05-18T09:04:13+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2026-04-27T09:26:09+00:00 7e670b7d6e10e5e072dfe05f425e635acec2524c Add UFS clock support for sc7280 including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add UFS clock support for sc7280 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: qcs615: Add UFS clock support 2026-05-18T09:04:13+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2026-04-27T09:26:08+00:00 213edfd64501fca1c9e62640b4b1b362a2fd486a Add UFS clock support for qcs615 including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add UFS clock support for qcs615 including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: sa8775p: Add UFS clock support 2026-05-18T09:04:13+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2026-04-27T09:26:07+00:00 4b1580e060847ce63b38a1f87bd482b60ec6523f Add UFS clock support for SA8775P including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add UFS clock support for SA8775P including register definitions,
rate configuration, and gate clocks.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk/qcom: Add Milos clock driver 2026-04-27T10:38:44+00:00 Luca Weiss luca.weiss@fairphone.com 2026-03-18T12:46:28+00:00 0661dc33050886f169192723feb301c8cee00a79 Add Clock driver for the GCC block found in the Milos SoC. The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref" clock), so we need to pass that as well. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://patch.msgid.link/20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add Clock driver for the GCC block found in the Milos SoC.

The qcom-snps-eusb2-hsphy driver requires the TCXO frequency ("ref"
clock), so we need to pass that as well.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260318-milos-bringup-v2-2-650b91dd75d8@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: sc7280: add missing SDCC1 clocks 2026-04-27T10:38:44+00:00 Ajit Singh blfizzyy@gmail.com 2026-02-26T19:32:17+00:00 16a16b55ce5fd75097bc07e7c0503b59b5401a81 Add GCC_SDCC1_AHB_CLK and GCC_SDCC1_APPS_CLK gate clocks. Required on platforms where SDCC1 is used for eMMC. Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=a3cc092196ef63570c8744c3ac88c3c6c67ab44b Signed-off-by: Ajit Singh <blfizzyy@gmail.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://patch.msgid.link/20260226193217.82657-1-blfizzyy@gmail.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add GCC_SDCC1_AHB_CLK and GCC_SDCC1_APPS_CLK gate clocks.
Required on platforms where SDCC1 is used for eMMC.

Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=a3cc092196ef63570c8744c3ac88c3c6c67ab44b

Signed-off-by: Ajit Singh <blfizzyy@gmail.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260226193217.82657-1-blfizzyy@gmail.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
drivers: clk: qcom: sc7280: Add USB3 PHY pipe clock 2026-04-27T10:33:30+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2025-12-03T11:07:30+00:00 c808ab5fed990e2aa8e4ca6a855db49a225edd64 Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by the USB3 PHY on SC7280/QCM6490 platforms. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://patch.msgid.link/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by
the USB3 PHY on SC7280/QCM6490 platforms.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support 2026-03-24T10:34:58+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2026-02-13T09:01:19+00:00 c4169dfa1dcc2dc4876b10e1b1dc3de6b96ffd80 Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
clk: qcom: qcs615: Add GCC_USB3_PRIM_CLKREF_CLK support 2026-03-24T10:34:58+00:00 Balaji Selvanathan balaji.selvanathan@oss.qualcomm.com 2026-02-13T09:01:18+00:00 c4f40d092590a7b4649d354c810114d5041f8cca Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver. This clock is referenced in the device tree USB node but was not implemented in U-Boot, causing "Clock 152 not found" warnings during fastboot run. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org> 
Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
This clock is referenced in the device tree USB node but was not
implemented in U-Boot, causing "Clock 152 not found" warnings during
fastboot run.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>