u-boot.git/drivers/clk/qcom, branch v2024.07

Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""

2024-05-19T14:16:36Z

When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman Signed-off-by: Tom Rini

clk: Remove and add needed includes

2024-05-07T14:00:41Z

Remove from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini

apq8016: Add support for UART1 clocks and pinmux

2024-04-23T11:29:22Z

SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly Signed-off-by: Sumit Garg Signed-off-by: Caleb Connolly

clk/qcom: ipq4019: return valid rate when setting UART clock

2024-04-23T11:29:15Z

clk_set_rate() should return the clock rate that was set. The IPQ4019 clock driver doesn't set any rates yet but it should still return the expected value so that drivers can work properly. For a baud rate of 115200 with an expected bit clock divisor of 16, the clock rate should be 1843200 so return that frequency. Signed-off-by: Caleb Connolly

clk/qcom: apq8016: return valid rate when setting UART clock

2024-04-23T11:29:14Z

The clk_init_uart() helper always returns 0, but we're meant to return a real clock rate. Given that we hardcode 115200 baud, just return the clock rate that we set. Signed-off-by: Caleb Connolly

clk: qcom: Add SM8650 clock driver

2024-04-23T11:29:11Z

Add the GCC and TCSRCC clock driver for the SM8650 SoC. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. Signed-off-by: Neil Armstrong Reviewed-by: Caleb Connolly Signed-off-by: Caleb Connolly

clk: qcom: Add SM8550 clock driver

2024-04-23T11:29:10Z

Add the GCC and TCSRCC clock driver for the SM8550 SoC. The GCC driver uses the clk-qcom infrastructure to support GDSCs, Resets and gates. While the TCSRCC is a simpler clock driver which only supports gates. The GCC enable and set_rate callbacks contains some tweaks to setup clocks for Debug UART, SDCard controller and USB. The TCSRCC gates returns the XO frequency, which is used by the Synopsys eUSB2 driver to determine the PHY configuration. Signed-off-by: Neil Armstrong Reviewed-by: Caleb Connolly Signed-off-by: Caleb Connolly

clk/qcom: sdm845: enable SDCC2 core clock

2024-04-23T11:29:08Z

Allow setting the clock rate for the SD card core clock. This is required for SD card support on SDM845 devices. Signed-off-by: Caleb Connolly

clk/qcom: add driver for sm8250 GCC

2024-04-23T11:29:05Z

Add a clock driver for the SM8250 SoC. This driver can enable necessary clocks for UART, UFS, USB, and MMC. Signed-off-by: Caleb Connolly

clk/qcom: add driver for sm6115 GCC

2024-04-23T11:29:04Z

Add a driver for the clock controller in the SM6115 SoC, this is used in the QRB4210 RB2 board. Signed-off-by: Caleb Connolly