u-boot.git/drivers/clk/qcom, branch v2025.01

clk/qcom: sm8250: add debug data

2024-10-04T12:57:04Z

Drop in the RCG and GPLL data for debugging these clocks. Signed-off-by: Caleb Connolly

clk/qcom: sm6115: add debug data

2024-10-04T12:57:04Z

Add "clk dump" support for SM6115. Signed-off-by: Caleb Connolly

clk/qcom: sdm845: add dump data

2024-10-04T12:57:03Z

Add debug data to dump PLL and RCG clocks. Signed-off-by: Caleb Connolly

clk/qcom: implement clk dump

2024-10-04T12:57:03Z

Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-.c. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. Signed-off-by: Caleb Connolly

clk: qcom: add driver for SM8150 SoC

2024-10-04T12:57:01Z

Add clock, reset and power domain driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This driver supports clock rate setting only debug UART, RGMII/Ethernet modules and USB controller. Co-authored-by: Volodymyr Babchuk Reviewed-by: Caleb Connolly Signed-off-by: Julius Lehmann Reviewed-by: Neil Armstrong

clk/qcom: add initial clock driver for sc7280

2024-09-06T08:47:46Z

We don't actually need any clocks to get UFS up and running, resets are useful though. Reviewed-by: Neil Armstrong Reviewed-by: Simon Glass Signed-off-by: Caleb Connolly

clock: qcom: ipq4019: add missing networking resets

2024-07-25T23:53:12Z

IPQ4019 has more networking related resets that will be required for future wired networking support, so lets add them. This syncs the driver with Linux. Signed-off-by: Robert Marko Reviewed-by: Caleb Connolly

clock: qcom: ipq4019: add ESS clock

2024-07-25T23:53:11Z

ESS clock is the Ethernet Subsystem clock, so lets add it as its already configured by SBL1. Signed-off-by: Robert Marko Reviewed-by: Caleb Connolly Reviewed-by: Sumit Garg

drivers: clk: Remove duplicate newlines

2024-07-22T16:53:04Z

Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut

Merge branch 'qcom-main' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon

2024-07-05T16:24:27Z

Various minor fixes and improvements: * Fix Qualcomm SPMI v5 support * Move default environment to a file * Add support for special pins (e.g ufs/mmc reset/data pins) * IPQ moves to OF_UPSTREAM and receives some cleanup and MAINTAINERS changes * Add a reset driver for devices without PSCI * msm8916 USB clock improvements for mobile devices